Design Of FPGA-Based Video Image Edge Real-Time Detection System

Extracting image edges is the basis of image processing algorithms,and is of great significance for image edge extraction.Nowadays,video image data is developing in the direction of high resolution and high frame number,which greatly increases the amount of image data and the difficulty of processing.Since traditional software processing is a serial structure processing method,the processing speed is limited,and it is difficult to ensure high reliability and real-time performance in some image processing applications that require high processing speed.FPGA technology stands out because of its parallel processing and pipeline structure,it can complete high-speed processing of large amounts of image data.The higher processing speed ensures the real-time nature of image data processing.The application of FPGA technology in the field of image data processing will be unprecedented.This design uses the Cyclone ? E series FPGA main control chip and verilog HDL hardware description language to process the real-time edge detection algorithm of image data at 640 × 480 resolution and 40 frames /second in the video image color image collected by the camera OV5640.Finally,the edges of the extracted video images are sent to the host computer for real-time display through 100 M Ethernet.The FPGA-based video image edge real-time detection system can be applied to the field of dynamic feature recognition,such as face recognition,number plate recognition on traffic roads and other occasions that require high image frame numbers.The main FPGA implementation module of this design includes IIC protocol driver and configuration,image data acquisition and conversion,image edge detection,SDRAM controller,image data encapsulation,and UDP protocol upload.The required external equipment is equipped with a camera OV5640,SDRAM external memory,and a host computer.The host computer needs to be connected to the FPGA by the RJ45 crystal head,that is,the network cable supported by the PHY chip(the Ethernet MAC layer and the PHY chip interface are MII interfaces).The characteristic of this system is that the processing matrix template of the traditional Sobel edge detection algorithm is improved by matrix coefficients,and the image noise is filtered at the same time.Finally,the detected edge image is passed through the Ethernet multi-layer protocol(the bottom layer is UDP protocol)It is sent to the host computer for real-time display.The networking operation with the host computer is to further complete the subsequent image processing algorithm,which can be further processed using traditional software or FPGA,and has strong operability.