Design And Implementation Of Front End Of 2.45GHz RFID Analog RF Receiver

As an emerging automatic identification technology,UHF radio frequency identification(RFID)technology has been rapidly popularized at home and abroad.RFID has the characteristics of fast communication speed,strong penetrability,multiple reading and writing,large data storage capacity,low cost,small size and convenient use.It is widely used in various fields of society.The analog RF receiver front end is a core module of RFID and has high scientific and engineering value.In order to realize the localization of core components,improve component reliability and mass production capacity,the thesis based on the development of the national standard active 2.45 GHz RFID transceiver chip,this thesis takes the analog RF receiver front-end circuit structure and performance indicators as the main research object.It adopts zero-IF receiver structure,designs in SMIC RF 0.18 um CMOS technology,uses Cadence Spectre RF simulation software to design low noise amplifier,down converter,RF amplifier and other auxiliary circuits,and complete the pre-simulation and post-simulation,and finally successfully streamed.The main research contents are:1.Studying the principle of high performance low noise amplifier,designing a high gain,low power and low noise amplifier structure.The circuit uses a single-ended input structure that uses an inductor for the load and a differential output for the next stage RF amplifier.The input terminal adjusts the gain step by changing the magnitude of the tail current;the output terminal is connected in parallel with a variable capacitor for adjusting the resonant frequency during the test.The circuit has two working modes of amplification and through,and does not consume current in the through mode,which can save power and improve linearity.2.Studying the principle of high-performance down-converter,using the traditional double-balanced Gilbert structural unit to design a down-converter.The switching transistor of the circuit adopts a differential PMOS transistor structure,and the output terminal can change the tail current source size by digital control,thereby adjusting the linearity of the mixer。3.Studying the auxiliary circuit of the front end of the RF receiver.A series of unit circuits such as RF amplifier,local oscillator buffer amplifier,reference circuit,DC trimming circuit and anti-aliasing filter are designed.4.Studying the principle of high-performance layout knowledge of high-performance RF circuits.The reliability design of the chip is introduced.The layout design and post-simulation of each module are completed in combination with the schematic diagram.The whole chip package and RF receiver test are also introduced.The test results show that the RF receiver front-end circuit module operates at 2394MHz~2507MHz,the channel's typical operating voltage is 1.8V,the RF input standing wave is-27.3dB,the maximum gain is 36.4dB,the double-side noise figure is 6.7dB,the input 1dB compressed point power is-39 dBm and the I/Q amplitude error is 1.7dB.