| As one of the most effective algorithms for realizing artificial intelligence tasks,CNNs(Convolutional Neural Networks)have been widely used in various scenes.So far,the platforms to accelerate the CNNs mainly include General Purpose Processor and ASIC(Application Specific Integrated Circuit).The former performs better in flexibility,but the computational efficiency and power consumption cost.While the latter performs better in computational efficiency,but it has higher development costs.The ASIP(Application Specific Instruction Set Processor)optimizes a specific application domain,compared to ASIC,it sacrifices certain performance to increase flexibility,so that a balance can been reached between performance and flexibility.TTA(Transport Triggered Architecture)is a kind of architecture in ASIP.It treats register units as a special function unit,which can effectively reduce the design complexity of the register files and make it become a superb processor for specific domain.This paper first designs a computational framework for the TTA processor,which enables the processor to accelerate the CNNs with any depth.At the same time,input-buffer optimization structure and output-buffer optimization structure are proposed for optimizing the insufficient on-chip storage resources,reducing nearly half of the storage resources.Secondly,the computational efficiency of the traditional convolution function unit is very low when the stride parameter is greater than 1,also,it costs too much on-chip memory resources.A rotary-storage structure is designed for this to solve this problem without increasing the computing and on-chip memory resources,so that computational efficiency can be increased and usage of on-chip memory can be reduced.Furthermore,due to the complexity of computing procedure of CNNs,this paper designs the functional units and interconnection networks of TTA processors based on TCE toolchain from large scale to reduce processor complexity and increase computational efficiency.Finally,start from the flexibility of the processor,each operation layer is encapsulated,which can achieve acceleration under arbitrary parameters.The acceleration of specific layer can be achieved in the software with a simple function call.This paper designs the TTA processor of the CNNs,which greatly reduces the development time and the cost of the hardware acceleration platform.At the same time,compared to CPU,TTA processor can achieve high computationally efficient,furthermore,less load-store times are needed,which means better performance. |
