Design Of 3GSPS DAC Parallel Pseudo Interpolation Waveform Synthesis Module

Broadband waveform generators are more and more widely used in the electronic information testing industry due to their large signal bandwidth and high-quality output waveforms.With the rapid development of the testing industry,the requirements for the output bandwidth of broadband waveform generators are becoming higher.The sampling rate of the digital-to-analog converter in the waveform generator,as one of the main constraints of the output bandwidth,has been unable to meet the demand.Pseudo-interpolation technology using multi-channel DAC parallel structure can solve this problem well,and achieve the multiplication of DAC sampling rate.This article uses two DAC chips with a maximum sampling rate of 1.5GSPS replaced a 3GSPS DAC chip to implement a pseudo-interpolation waveform synthesis module with an equivalent sampling rate of 3GSPS,so that a 1.5GSPS sampling rate DAC can output waveforms up to 800 MHz.This paper focus on the design of high-speed synchronous hardware circuits and data synchronization output logic.Existing phase mismatch error and amplitude mismatch error were analyzed and tested in depth.The main research contents are as follows:1.Demonstrated the feasibility of DAC parallel pseudo-interpolated waveform synthesis,and analyzed in detail the effect of channel-to-channel mismatched,determined the structure of "FPGA+DAC+DDR3 SDRAM" to achieve waveform synthesis,and the circuit need to require the function of clock phase adjustment and output waveform amplitude adjustment.2.High-speed synchronous hardware circuit design.The emerging JESD204B high-speed data interface is used to achieve the interconnection between FPGA and DAC to transfer the data synchronously and avoid random phase problems caused by the LVDS interface.In the case of a clock frequency of 750MHz?1.5GHz,according to the requirements of the pseudo-interpolation module for the clock,a variety of clock generation and control methods are analyzed,and it is determined to use the "DDS+PLL" structure to achieve a high-frequency clock with variable frequency.The phase mismatch between the high-frequency clocks of the road is solved by a fan-out chip,whose delay adjustment step can reach 25 ps.Two symmetrically arranged DDR3 SDRAMs are used to store the waveform data required for pseudo-interpolation,so as to achieve the synchronous reading and writing of the waveform data.3.Data synchronization output logic design.In order to realize the synchronous and continuous output of two waveform data from FPGA,two completely symmetrical logic designs are adopted,and the data width and clock domain are converted through asynchronous FIFO to make the waveform data output continuously and stably.Using AXI4 DMA and JESD204B protocol as the core to design the waveform data sending end,and realize the synchronous output of dual-channel waveform data from FPGA.Through testing,the equivalent sampling rate range of the pseudo-interpolated waveform synthesis module designed in this paper is 1.5GSPS ? 3GSPS;the maximum output bandwidth is 800MHz;the spurious-free dynamic range in the bandwidth is greater than 30dBc;The maximum memory depth is 1GSa/channel.