The Implementation Of Communication Function On Time Triggered Network Node Card

In many new information networks such as vehicle networks,military industries,and avionics,the concept of time triggered has been proposed in earlier years.In order to meet the high-performance requirements of the network for real-time and reliability,it has been a significant development trend to add the time scheduling function to the distributed network node card,and some professional and technical departments abroad have achieved some results.Based on the analysis of the theory and results of time scheduling networks and node cards,this paper decides to combine the Ethernet node card with the time scheduling function,and to realize the communication function of the time triggered network node card as the research goal.This paper is based on the traditional Ethernet node card architecture,adding time synchronization function modules,integrates the time-triggered receiving and sending functions based on the time schedule in the data transmitting and receiving part.According to this design,it can not only keep the normal transmission and reception functions of Ethernet for traditional data,but also meet the requirements of specific industrial fields for real-time data transmission.At the same time,the conflict of different scheduling services is considered,and a multi-service and multi-cache method is adopted.An arbitration mechanism that reads the scheduling table is introduced.The ET priority back-off mechanism of TT also ensures the complete transmission of traditional ET data and TT data.On the other hand,since the PCIe bus and the AXI bus are both currently widely concerned bus structures,in the DMA data exchange part,this paper conducts research and development of communication modes based on these two buses.The main body of the paper is divided into two parts.The first part is the logic update of the time synchronization and time scheduling sending and receiving functions required in the TTE network for the logic of traditional Ethernet node cards processing Ethernet frames at the link layer.The second part is to achieve data communication through DMA and software memory space,focusing on the logic implementation under the AXI bus standard.The overall design of this thesis relies on Xilinx's FPGA development platform,with the node card scheduling function in the time synchronization state as the design goal,and the corresponding complete engineering development is carried out.After all the design schemes are completed,use the modelsim simulation software to simulate and verify the logic function of the link layer firstly,and then use the related software to perform board-level data transmission and reception tests,and use vivado to capture the signals to complete the DMA function to achieve the data Development goals for communications.