Full SiC Power Module Reliability Research

With the development of the third-generation semiconductor technology,silicon carbide(SiC),as one of the important representatives,has been widely used and developed in new energy generation,smart grid power conversion,transportation electrification and other fields.Compared with the traditional Si-based insulator gate bipolar transistor(IGBT)modules,SiC-based power modules have excellent high temperature and high frequency characteristics,good heat transfer and lower power loss,which have gradually become a potential substitute for Si-based devices,especially in high-power applications around 10 k V.Among them,the research and development of SiC power modules have attracted much attention,but the high failure rate and low reliability problems associated with high power density modules cannot be ignored.The reliability of full-SiC power modules is studied from the perspective of module package reliability.First,it summarizes the currently proposed package structures suitable for SiC power modules.Then,the finite element model was established for three different double-sided cooling package structures and the commercial package structure commonly used in SiC modules.And their temperature field,strain field and lifetime are compared and analyzed by multiphysics field simulation.One of the 3D double-sided cooling structures exhibits good thermal reliability.It not only lowered the junction temperature by using a single heat source but also reduced the stress and strain of the chip and the solder layer,respectively,by nearly 30% less than the single-sided cooling structure.In addition,the fatigue life of the solder under thermal cycling was significantly longer than in the other structures.In order to further improve the operational stability,to ensure the thermo-electric reliability of the module.This article has improved the 1.2k V/200 A 3D double-sided cooling package structure layout to reduce the internal parasitic inductance.The design is to sinter the chips on two symmetrical direct bounded copper(DBC)substrates,respectively,to provide a commutation loop path that occurs simultaneously on two DBCs.This method effectively expands the horizontal and vertical distances and related heat dissipation area of each chip,so that the thermal coupling effect between the chips is well alleviated.And the parasitic inductance on the maximum commutation loop of the optimized layout structure is only 1.56 n H,which reduces the adverse effect on the switching performance as much as possible.And compared with the original layout design,the proposed layout also reduces the maximum junction temperature by more than 22%.In this paper,a reliability-related horizontal comparison of the package structure designed for SiC power modules is made,which more intuitively reflects the reliability of different package structures,and optimizes the DBC layout of the package structure.It provides a certain reference for the design and optimization of the subsequent advanced packaging structure.