Accelerator Design And Research Of Convolutional Neural Network In Speech Recognition

In recent years,speech recognition technology has made great progress.In the mobile terminal,its extensive application brings convenience to people's life and work.At the same time,convolutional neural network plays an important role in speech recognition inference calculation,and convolutional neural network forward inference calculation often requires hundreds of millions of floating-point calculations and the storage of floating point parameters,so how to hardware accelerate the convolutional neural network in speech recognition has become a challenge.This article first introduces the main model of speech recognition,analyzes the convolutional neural network in speech recognition,structural characteristics,according to the characteristics of network design and the corresponding operation circuit module,the combination of software and hardware integration design,realized the convolutional neural network accelerating algorithm in speech recognition,finally in this paper,the FPGA design of their own,It has certain advantages in performance.Aiming at the 17-layer convolutional neural network model of speech recognition,this paper uses hardware description language to carry out forward reasoning.The computing module includes multiplication and accumulation module,convolution module,pooling module and full connection,etc.The top-level module connects all the computing modules to realize the forward reasoning calculation of convolutional neural network.ARM is used to realize the control of CNN accelerator's calculation flow and the interactive control of stored data.The weight of the network is quantized to 8 bit fixed point number to improve the processing performance.In this paper,a configurable computing architecture is proposed to improve the adaptability of the architecture.In this paper,the data weights used in each layer of computing are stored in PL,which maximizes the utilization of on-chip cache resources.In this paper,a parallel computing method is used to improve the performance of the accelerator.Verification is realized on Zynq series FPGA board.Under the 200MHz system clock,the computing speed of 143.96GOP/S is achieved,and the power consumption is 16.681W.