Accuracy Controllable BCNN VLSI Architecture And Circuit Design For Common Word Recognition

Online voice is becoming a popular form of human-computer interaction,especially for wearable devices,the Internet of Things,and so on.Ultra-low power and real-time processing are critical to these battery-powered devices.The deep neural network(DNN)has achieved great success in speech recognition,but its huge parameters and calculations generate excessive power consumption.Binary Convolutional Neural Networks(BCNN)can be used for speech recognition to reduce storage overhead and power consumption,and also introduce 10.0% relative accuracy loss.Based on BCNN,this paper proposes a speech recognition processor,which uses a digital-analog hybrid operation unit and an optimized calculation flow to achieve ultra-low power consumption.Secondly,an adaptive data bit width adjustment scheme is designed to further save energy.In order to compensate for the loss of precision,on-chip pre-training and multiple precision control strategies are designed.The main work of the thesis includes:(1)Designing an energy-efficient reconfigurable BCNN accelerator architecture for speech recognition based on convolutional neural networks.The processing unit included in the BCNN Accelerator supports digital-analog hybrid approximation calculations.This work can further improve the energy efficiency of the BCNN accelerator compared to the traditional digital approximate computing architecture.In addition,unlike the traditional analog computing architecture,the work of this paper can guarantee good recognition accuracy in various scenarios with different noise types and different SNR.(2)The design of the adaptive bit width adjustment calculation unit and the delay-based accumulation unit architecture,and their approximate calculation circuits for BCNN common word recognition are realized.It can dynamically reconfigure the data bit width of the computing unit to accommodate different computational accuracy requirements.Energy consumption can be significantly reduced compared to standard computing units.Based on TSMC 28 nm CMOS technology,the precision controllable BCNN VLSI architecture and circuit design for common word recognition is completed and the tape is completed.The simulation results show that the power consumption can reach 78μW at the TT process angle and 25°C,and the peak energy efficiency reaches 163TOPS/W.Under different noise backgrounds,the recognition rate can reach 93.6%.