Research On Mapping And Fault-tolerant Mechanism For Coarse-grained Reconfigurable Computing System

The coarse-grained reconfigurable system architecture is a new computing platform because it has high computational efficiency and low power consumption,so it has attracted much attention.However,the current research on mapping and fault tolerance of CGRA are still in the exploratory stage,and they still have many problems that need to be solved,such as the breadth of greedy mapping and depth-first greedy mapping of reconfigurable cell arrays,fault tolerance of data transmission between execution units,etc.This article has carried on the thorough research to these questions,its main work and the innovation points are as follows:(1)According to the problem of two-dimensional coarse-grained processing unit array to maximize the degree of parallelism and effective use of a single reconfigurable execution unit,a breadth greedy mapping algorithm is proposed.The algorithm is based on the circular data flow graph of computationally intensive tasks.It starts scanning with the first node,in accordance with the constraint conditions such as the size of the processing unit array and the interconnection relationship,the nodes that meet the hardware requirements are mapped to the processing unit arrayin turn.When encountering a node that does not satisfy the mapping condition,the algorithm skips the node and continues searching for nodes that satisfy the constraint for greedy mapping.The experimental results show that compared with Breadth No Greedy Mapping Algorithm(BNGMA),the BGMA achieves better optimization in terms of the configuration time and the total execution delay,satisfy the hardware constraints under the same system architecture,the CCON decreased by15.7%(PEA6*6)and 26.2%(PEA8*8)on average,and the total delay of TTOTAL was reduced by 20.2%(PEA6*6)and 32.1%(PEA8*8).(2)In order to reduce communication costs and the number of processing unit arrays that be used,a depth-first greedy mapping algorithm is proposed in this dissertation.The proposed algorithm considers both the communication cost and the number of processing unit arrays used,Compared with the layer mapping algorithm,the algorithm is better improved.The average percentage of total TTOTAL improvement is10%(PEA6*7)and 8%(PEA7*8).Compared with the layer depth mapping algorithm,This algorithm could also obtain the smallest average value of the communication cost,the number of partitions,the configuration time,and the total execution delay based on the same reference program,.(3)Aiming at the problem of fault-tolerance mechanism for coarse-grained reconfigurable computing systems,after doing in-depth study of relevant literature at home and abroad in recent years,masteredthe research and development status of fault-tolerant technologies at home and abroad.The method of reconfigurable chip-level fault location and repair is analyzed,and it is pointed out that the traditional redundancy technology will cause large hardware overhead and other defects,Analyze the principle and advantages and disadvantages of the typical fault-tolerant solutions.Based on a careful study of existing literature,the CRC(Cyclic Redundancy Check)method,which is commonly used in the field of information technology,is applied to the problem of fault tolerance in data transmission of two-dimensional coarse-grained processing unit arrays,and uses the electronic design automation software Modelsim to carry out the design and simulation verification of the relevant modules,Experimental results show that under the condition of choosing the proper generator polynomial,this method can accurately detect whether bit errors occur during data transmission.If the error bit is 1 bit,the method can not only detect whether the data transmission error occurs,but also locate the error bit in the reconfigurable execution unit,so as to achieve the purpose of error correction.Finally,the conclusions are given and the direction of further work is briefly discussed.