Design And Implementation Of 100Gb/s Ethernet Multi-link Gearbox Circuit

In recent years,with the emergence of a large number of Internet applications,the demand for high rate Ethernet has become stronger.Nowadays,the 100Gb/s Ethernet standard has been formed,which greatly promotes the rate and efficiency of data transmission.Currently,in the data center application,the new Ethernet architecture has gradually become 4?25Gb/s mode.However,the previous 10Gb/s and 40Gb/s network devices still exist in large numbers.In order to improve equipment utilization and achieve conversion of multiple rate ports to 4?25Gb/s,the Optical Internetworking Forum promulgated the Multi-link Gearbox(MLG-2.0)protocol in 2013.This enables a variety of applications to reuse 100GBASE-R technology for the transport of individual 10 G and 40 G links.This paper studies the Multi-link Gearbox technology that satisfies the 100Gb/s Ethernet MLG-2.0 protocol,focusing on the design and implementation of 10?10Gb/s or 2?10Gb/s+2?40Gb/s to 4?25Gb/s conversion.Firstly,the contents of 100Gb/s Ethernet and MLG-2.0 protocol are introduced.The similarities and differences are analyzed between the 10-GbE and 40-GbE processing units.On this basis,the design of TX MLG-2.0 circuit is completed,including idle deletion and insertion,interleaving,scrambling,block distribution and alignment insertion module.Through the design of the idle deletion module,the problem of different rate between input and output in different clock domains is solved.In order to reserve space for the alignment insertion module,a method of inserting an idle every 16383 blocks is adopted,enhancing circuit reliability and stability greatly.The scrambler is designed with a parallel scrambler structure inserted into the register to improve the processing speed of the scrambler.The block distribution module realizes the function of distributing 10GBASE-R signals to two MLG channels through the design of the serial input parallel output shift register.In the 40-GbE processing unit,in order to achieve high rate transmission,the 40Gb/s data is decelerated in advance,the data is distributed into four parallel data,and the data is interleaved for overall descrambling.Finally,the RTL design of the TX MLG-2.0 circuit is completed,and the correctness of each module is verified.Finally,this paper performs FPGA verification on the completed TX MLG-2.0 circuit on Xilinx's Vivado platform.After timing constraints,synthesis and optimization,the timing simulation results after placing and routing show that the MLG-2.0 circuit designed in this paper can work correctly at the frequency of 156.25 MHz under both mapping modes of 10?10Gb/s to 4?25Gb/s and 2?10Gb/s+2?40Gb/s to 4?25Gb/s to meet functional and timing requirements.