Design And Implementation Of Space Multi-channel Video Compression System Based On Single Link FPGA+DSP

With the development of space technology, the exploration of space also will move towards a higher level. Obtaining information such as texts and sounds can’t satisfy the needs, observing outer space scene with vivid video is desired. Meanwhile, with the continuous releasing of video standards, video compression technology which contributes a lot in the field of aerospace applications has become an indispensable key technology. Application of video compression technology can acquire video image efficiently, store information with less the amount of storage channel and improve transmission efficiency, which is helpful in interaction between spacecraft and the ground control system and real-time observation of outer space conditions. Scenes needed to be observed increase with the deep exploration of space. Shenzhou 9 spacecraft for example, there are both cabin and extravehicular scene. If the compression devices and transmission channels increase with the addition of observed scene, the system will become very huge, which results in video information acquisition enormous challenges.This paper proposes a kind of space multi-channel videos compression system design and implementation based on single link FPGA + DSP in consideration of the complexity and costs of the system, which aims at the condition that there are multi-channel video in aerospace applications. This proposal can reduce the complexity of the system greatly by compressing multi-channel videos in one hardware link and displaying separately. The main contents are as follows:First of all, the development and application of video compression and FPGA+DSP structure in space technology are outlined. Then all of the algorithms used in this design are analyzed, including the development of video compression standards, the coding framework and technical advantages in hardware implementation of H.264, color interpolation, color space conversion, histogram equalization and MIL STD 1553 B.A replaceable resource histogram equalization structure is proposed, aiming at the inadequate of register or RAM resources because of histogram equalization algorithm takes a lot. This structure can balance the usage of register and RAM resources dynamic, which results in better result in code synthesis.The implementation of this program on single link FPGA+DSP architectures is put forward based on the analysis above, including the overall system design, module division, the function and implementation of each module and reliability analysis of key modules.Finally, the bit-file is downloaded into the hardware platform for test and debugging after coding Verilog, simulation and comprehensive and layout. The design proposed can implement five video compression and transmission real-time in corresponding hardware.