Design Of True Time Delay Array Based On Digital Control

The true-time delay line can delay the signal for a period of time to meet the system's requirements for signal time domain and phase.Therefore,it is widely used in ultra-wideband beamforming systems to provide true-time delay compensation for the signal.With the demand for more refined scanning angles of phased array radars,higher requirements are also placed on the delay precision and delay range of the true-time delay line.To make true-time delay lines better used in ultra-wideband transmitters,it is of great significance to study a multi-channel true-time delay array that takes into account both high delay precision and wide delay range.Based on the index requirements of delay precision and delay range,this paper designs a digitally controlled adjustable true-time delay array circuit.The delay array has four outputs,which can achieve a fixed relative delay between adjacent channels.The delay array is divided into 3 modules:a four-channel array composed of cascaded active delay units,2 digital control circuits and 4 multiplexers.The delay array adopts a voltage-controlled adjustment delay unit,instead of the traditional adjustment method based on the path selection switch.The improved delay array structure reduces the requirements for the delay range of the unit and achieves a balance between delay precision and delay range.The active delay unit adopts an improved current starved inverter structure,which can achieve full swing output and has a larger adjustable delay range.The control voltage of the delay unit is generated by a 4-bit binary digital control circuit,which is constructed with a non-linear current type DAC structure,which can realize linear adjustment of the relative delay precision.The multiplexer is composed of logic gates,which determines the final output of the array and achieves the purpose of extending the relative delay range.To further simplify the circuit structure,the delay unit sharing technology is introduced to minimize the number of delay units in the array and effectively reduce the chip area.The circuit adopts TSMC 40nm CMOS process for layout design,and the final chip area is 0.2576mm~2.The post-simulation results show that under the TT process angle,the working frequency band of the delay array is 0.5GHz?4GHz,and the relative delay precision of 1.46ps can be achieved between adjacent channels.Under the adjustment of the 4-bit binary control signal,the entire delay circuit can reach a relative delay range of 0?45.29ps.The delay array has high delay flatness,the delay jitter of relative delay is less than1.71%,and the relative delay error between adjacent channels is less than 1.48%.For a phased array antenna with an element spacing of 5 cm,a scanning precision of 0.502°can be achieved.The S11 and S22 parameters of the circuit are both less than-10d B,and the input and output match well.The delay array has good amplitude characteristics,group delay characteristics and low attenuation characteristics.