Research And Design Of High Speed And High-Resolution DAC Based On CMOS/InP Heterogeneous Integration

Digital-to-analog signal converter(DAC),which links the digital and analog world,is an important part of the transceiver circuit.With the rapid development of modern mobile communication technology and integrated circuit technology,higher-accuracy,higher-speed,higher-bandwidth and lower-cost DACs is required.Heterogeneous integration technology obtains the advantages of III-V compound semiconductors and silicon-based CMOS devices,which realizes this DAC,and adapts to the development of three-dimensional stacking and micro-systemization of chips.This thesis synthesizes the common DAC structure and different heterogeneous integration process to conduct feasibility analysis.According to the analysis,a heterogeneous integration scheme based on micro-assembled die-to-die(D2D)and In P flip-chip packaging on CMOS is selected.In circuit design,CMOS devices are used to design digital circuits.A true single clock(TSPC)combined with static logic is used to simplify the scale of digital logic circuits,and improve the ability of this part of the circuit to process high-speed logic signals.While In P devices are used to design analog circuits.Emitter-coupled(ECL)circuit logic is used to build high-speed master-slave latches to resynchronize digital signals transmitted from CMOS.Due to the limitation of In P integration,the DAC is segmented into four most significant bits(MSBs)with thermometer unbinary code,and eight low LSBs with binary code by an R-2R ladder.This current-steering structure makes the tail current the same weight and reduces the mismatch.Through the allocation of circuit modules and the selection of devices,the low power consumption,high integration and good digital characteristics of the CMOS technology are fully utilized.It also takes advantage of In P technology's high analog output swing and excellent high-frequency characteristics,which realizes the complementary advantages of CMOS/In P.In this thesis,the heterogeneous interconnection(HIC)in CMOS/In P Heterogeneous Integrated DAC is studied.In terms of circuit function,it realizes the transmission of signals between CMOS and In P.To solve the problem of parasitic effect and signal integrity in the transmission path,the differential current mode circuit is used to transmit the signal.In terms of heat dissipation,HIC builds an efficient heat dissipation channel between In P substrate and Si substrate for HBT heat source,but the increase of HIC leads to the decrease of heterogeneous integration yield.In this thesis,by using a simplified CMOS/In P heterogeneous integrated geometric model,combined with the finite element method,a thermal resistance network analysis model is established to conduct steadystate thermal simulation studies and summarize the heat dissipation characteristics of HIC.In the chip design,the number and distribution of HICs are optimized to achieve a compromise between chip temperature and yield.This thesis presents a 12-bit,2GSPS DAC chip with dual channels in heterogeneous integration process of SMIC 0.18?m standard CMOS and 0.7?m standard In P technology.The dual-channel differential signal is received by LVDS and compounded by 2: 1 MUX to achieve a sampling rate of 2Gsps.It adopts 4+8 segment decoding method,that is,the 4 MSBs use thermometer decode and 8 LSBs use binary weighted decode to achieve a balance between performance and area.In the circuit,the digital power supply is 1.8V and the analog power supply is 3.3V.The simulation results show that INL is 0.26 LSB and DNL is 0.6LSB.The SFDR at the Nyquist frequency is 54.74 d B.The establishment time of the system is 4.92 ns and the total power consumption is about 1.81 W.The area of the In P chip is about 3.5mm × 1.6mm,and the area of the CMOS substrate is 4.5mm × 3.5mm.