Study On Non-voltage Domain ADC With Emphasizing On The Calibration Technology

With the rise of 5G,artificial intelligence,Internet of Things and other fields and the continuous improvement of semiconductor process technology,the traditional voltage domain ADC?Analog-to-Digital conversion,ADC?is facing a huge challenge brought by the proportional reduction.Therefore,the conversion mechanism and structure of non-voltage domain ADCs have received more and more attention,especially time domain ADCs and electronic interferometric ADCs.The ADCs of these two structures have obvious advantages over traditional voltage domain ADCs in terms of power consumption and speed.Among them,time domain ADCs can be realized more by digital circuits,so that the benefits of process development can be more fully utilized..At present,the main problem in these two structures is that the nonlinearity caused by the error makes the dynamic range greatly restricted.This article first introduces the working principle of the time domain ADC,and systematically analyzes its internal sources of error.According to the error characteristics of the VTC?Voltage-to-Time Converter,VTC?module and the TDC?Time-to-Digital Converter,TDC?module,the following measures to improve the dynamic range are proposed:?1?Put forward the idea of segmented calibration,use the code density test calibration method to extract and compensate the delay chain by segment;?2?Expand the TDC code density test algorithm,Use it for VTC nonlinear calibration;?3?Based on the randomness of the error,a DEM?Dynamic Element Matching,DEM?architecture is used.Multiple delay units are placed at each delay module,and each delay unit is randomly selected for access to each quantization.In the delay chain,the error is averaged,and the purpose of breaking harmonics and improving SFDR is achieved;?4?Using the randomness of the error,a method of constructing a cyclic delay chain to support the randomization of the time signal input position is proposed to achieve the dispersion of nonlinear harmonics and improve the SFDR.For LC interferometric ADC,this paper analyzes the principle of interference,establishes a simulation model,and derives the voltage expression at the lattice point;proposes a method to increase the effective quantization of information by controlling the initial phase of the interference signal source to break the central symmetry of the interference pattern.The circuit error is modeled and the effect of the error on the ADC performance is evaluated.Simulation and verification were carried out based on MATLAB/Simulink and Cadence.For a 4-bit,1.25GS/s time domain ADC,when f_in=600MHz,the segmented code density calibration can improve ENOB?Effective Number Of Bits,ENOB?from2.78bits to 3.76bits,and the SNDR?Spurious Free Dynamic Range,SFDR?is improved by 5.9d B;the method of calibrating the nonlinear error of VTC based on code density test can improve ENOB from 2.04bits to 3.95bits;DEM method and randomized cyclic delay chain can disperse harmonics to the noise floor,and the DEM design method can increase the SFDR?Spurious Free Dynamic Range,SFDR?from25.19d B to 35.04d B.Based on the 65nm CMOS process,a 16×16 LC array interference circuit is designed.When the input amplitude of the interference signal source is 50m V and C₀=8.9f F,L₀=64p H,the output interference voltage varies from 8m V to 160m V.Moreover,after changing the initial phase of the interference signal source,it can be observed that the interference pattern exhibits obvious asymmetric diversity,which is beneficial to the subsequent quantization and coding.