Research On ESD Protection Design And Characteristics Of Nanometer Integrated Circuits

Electrostatic discharge(ESD)is a common physical phenomenon that exists in almost every corner of life.The modern semiconductor technology is booming,and the reliability problem of integrated circuits(ICs)cannot be ignored.The ESD problem plays an important role in the reliability problem,which also makes ESD protection an integral part of the integrated circuit field.This paper is based on the research on two terminal chip projects under 28 nm process,and has made a detailed investigation on the common power port failure modes of one of the chips.Based on the failure analysis and failure mechanism,a corresponding protection solution is designed for the weak points of ESD protection.A new ESD device under the 14 nm Fin Fet process was designed and taped out.The main protection device of the power pin of another chip,RC NMOS,was researched for resistance defects including rising edge,power on and power off,and EOS surge.In addition,the performance of ESD devices under high voltage BCD process and Ga As process is designed and studied.The main contents and conclusions of this paper are as follows:1.According to a 28 nm CNMOS process terminal chip provided by the project,ESD testing and failure analysis were performed,and the specific failure modes of the chip were summarized.The weak point of ESD protection of the chip was that the on-chip protection device GGNMOS of the device was out of coordination with off-chip TVS protection Losing the clamping voltage ability damages the PMOS / NMOS output tube and the internal core circuit.Based on the failure analysis results and ESD test analysis,the failure mechanism is summarized and optimization suggestions are proposed.2.According to the new ESD device requirements under the Fin Fet process,combined with the design experience under the planar CMOS process,draw a layout of the new 14 nm ESD device and perform tape-out.Through current density simulation and TLP testing,the working mechanism of the device and ESD protection parameters are analyzed.The layout of the taped results was further optimized,and the overall results met the project indicators,providing design experience for the research team's future Fin Fet taped.3.Based on a terminal chip power pin ESD protection device-RC NMOS,analyzing the working mechanism of the RC NMOS.The experimental scheme of slow rising edge,power on and power off and EOS surge pulse in practical application scenarios is designed and simulated.Based on the experimental results of resistance defects and failure analysis,the working mechanism of RC NMOS in three test scenarios is studied,and the protection improvement plan is designed and verified by simulation for the risk points found.The ESD working model of RC NMOS in non-standard ESD application scenarios is established.4.Based on the existing ESD performance defect of LDMOS under the high-voltage BCD process,an improved LDMOS with NW at the drain was proposed.The test results of the tape show that the device's robustness is improved while retaining the LDMOS DC electrical characteristics;The LDMOS-SCR structure proposes a drain-terminal segmented LDMOS-SCR,which ensures the structural integrity and robustness of the device SCR while saving the layout area.5.For a Ga As PHEMT high-speed optical module power amplifier used in engineering,a full-chip robustness test was performed using HBM and TLP tests.The ESD failure mechanism and weak points were determined,and a Schottky diode string structure was proposed.The tape-out results shows that the HBM level of the chip's weak point VC pin was improved from 350 V to 750V.