Design And Research Of Computing-In-Memory Core Based On RRAM Array

In recent years,Artificial Intelligence(AI)represented by Deep Neural Networks(DNN),has achieved great success in wide application.But the computationally intensive and memory access intensive features of AI algorithms have led to a dramatic increase in the cost of computing and storage on hardware,especially in edge computing tasks,which is urgently requesting new processing units with a much higher computing-power-ratio.The Computing-In-Memory(CIM)architecture based on the emerging Non-Volatile Memory(NVM),with the integration of storage and computing,high density and large-scale parallel computing,is one of the most promising solutions to break the performance bottleneck of von Neumann architecture.However,the accuracy and efficiency of conventional CIM cores are not good,because of the nonlinearity of the resistive NVM and the conversion interfaces for analog computing.The dissertation analyzes the characteristics and problems of several conventional CIM cores,and proposes a circuit design of 8-bit robust CIM core based on RRAM array.First of all,the RRAM array scheme with 8-bit binary 1T1 R structure,fixed reading voltage and precise weighting circuit,is adopted to reduce the impact of the non-ideal characteristics of the RRAM devices on the weights and computing accuracy.Then,an integral multiplier is designed based on the integration and charge redistribution scheme,which achieves digital-to-analog conversion while completing the analog computing of Multiplication-and-Accumulation(MAC),and thus eliminating the conventional DAC interfaces.The proposed design also eliminates the reading deviation of RRAM devices due to the post-weighting method,which improves the accuracy and efficiency of CIM.A capacitors-shared Successive Approximation Register Analog-to-Digital Converter(SAR ADC)is also designed to improve the area utilization and conversion speed of the overall design by sharing the capacitor with the integral multiplier.Finally,a series of low-power and low-noise technologies are adopted to optimize the circuit design,and a brief overview of the mapping method is introduced.The circuit-level simulation results show that the proposed CIM core achieves 7.26 bit of Effective Number of Bits(ENOB)with 0.78 m W power consumption and 1.85 M/s computing speed.The proposed design is very robust to the nonlinearity of RRAM devices,process variations,voltage fluctuations and temperature variations(PVT).Furthermore,the system-level verification and energy consumption estimation are also performed based on circuit-level extracted parameters.Compared with previously reported CIM implementations and Deep Learning Accelerators(DLAs)(without CIM ability),the proposed design achieves 2.23x—7.26 x better energy efficiency in 8-bit high-precision mode,and achieves relatively high accuracy with Le Net and Alex Net.