The Design Of A Low Power And High Reliability RO PUF

In recent years,the physical unclonable function(PUF)based on the oscillation ring is applied to the security field such as key generation.The inherent physical characteristics determined by the process deviation make it generate different response bits under the same excitation,which improves the system security.At the same time,the circuit structure of physical unclonable function based on the oscillation ring is easy to implement on the FPGA platform and the ASIC platform,and the entropy value is easy to calculate.However,its power consumption is large,and reliability is susceptible to environmental factors(temperature)and aging.In this thesis,the ABRO with dynamic adjustment of substrate voltage and stress and the RO PUF architecture with high frequency difference are proposed from the circuit level and architecture level respectively,which can effectively reduce the influence of temperature and aging on reliability with less power consumption.The ABRO with dynamically adjusted substrate voltage and stress mainly adjusts the threshold voltage variation of the inverter in the oscillating ring by the substrate bias effect to offset the leakage current change caused by the temperature,and the stress adjustment unit is adjusted dynamically to make it not work sometime,which makes oscillating rings enter sleep state,reducing the stress duration of the oscillating ring's pull-up network,and the effective supply voltage is reduced by dynamic stress adjustment unit.The low power consumption and high frequency difference RO PUF architecture mainly uses the power supply voltage control module to lower the low frequency oscillation ring power supply voltage according to the initial response bit,so that the frequency curve of the low frequency oscillation ring moves down,increasing the frequency difference between the oscillation rings.And a proximity detection circuit is used to reject pairs of excitation responses that have a small difference in frequency.Thereby reducing the possibility of frequency crossover and improving reliability.Based on the SMIC 40 nm process,six RO PUF structural circuits(ABRO PUF?RO PUF,ARO PUF,BCO PUF,CS RO PUF and two FTL RO PUFs)are built in the Cadence Virtuoso environment.The Monte Carlo simulation of the process variation between the chips was used to collect the response bits.After processing with Matlab,the uniqueness and temperature reliability of the six RO PUFs were obtained.When simulating the impact of aging on reliability,the Relxpert simulator is used to extract the netlist after aging,and Monte Carlo simulation is performed on the netlist with and without aging parameters respectively.Finally,the Matlab program is used to calculate the aging reliability.Experiments show that the ABRO array with integrated substrate voltage and stress dynamic adjustment and the RO PUF of rchitecture with low power consumption and high frequency difference achieve 99.8% temperature reliability and 99.37% Aging reliability.Finally,in the SMIC 40 nm 1P7TM process,the top-level design of the integrated custom ABRO array and semi-custom test circuit is physically implemented,and the power consumption of each generated response bit is 34.98?W.Relative to CMOS,the power consumption of ABRO PUF is reduced by 87.24%.