Design And Implementation Of Bit-level Processing Parallel Architecture For 5G Physical Layer

The transformation of mobile communication technology injecte powerful impetus into economic development.The rapid popularization of mobile devices opene up new market areas through mobile communication technology,especially the fourth generation mobile communication system(4G).As mobile communication technology promotes the development of the digital economy,the demand for mobile communication systems is increasing,so the fifth generation mobile communication system(5G)came into being.In order to adapt to the needs of mobile communications between the next 10 years,5G makes a lot of changes in the mobile radio access network and core network of the basis of 4G.Furthermore,it needs to deploy some new technologies.The Radio-Access Technology used by 5G is also called NR(New Radio),which shows that high expectations are given to it.5G has a wide range of application scenarios and can meet the different needs of most businesses.There are three main highlights of its application scenarios,enhanced mobile broadband,massive machine type communications and ultrareliable low latency communications.At the same time,it brings great challenges to the physical layer data processing of radio access networks when adapting to many application scenarios.Traditional general-purpose processors can no longer meet the requirements of 5G physical layer data processing.This paper studied the parallel data processing methods of the physical uplink/downlink shared channel in the NR physical layer.The parallel data processing architecture based on Field Programmable Gate Array(FPGA)supporting multiple deployment methods has not only been designed,but also implemented on Xilinx ZYNQ Ultra Scale + RFSo C XZCU21 DR.According to the frequency band and antenna configuration used by the base station,the paper has analyzed the throughput requirements of the bit-level data parallel processing in physical uplink / downlink shared channels under a single carrier.Firstly,starting with throughput requirements and taking into account both versatility and scalability,the same data communication interface is designed for two different physical channels to adapt to different deployment scenarios.According to various factors,for example,the characteristics of the physical channel input and output data types,the available resources of the hardware platform,data throughput requirements,implementation complexity,the two physical channel bit-level parallel data processing architecture is designed.Then,according to the characteristics of FPGA devices,the implementation method of parallel data processing architecture on FPGA platform is introduced in detail.After that the designed bit-level parallel data processing engine is tested.The test is divided into two parts,simulation test and deployment test based on hardware platform.Drawing on the method in the Verification Methodology Manual,using the method based on functional coverage to test the parallel data processing engine.According to this method,two common simulation frameworks for different physical channels are designed,and corresponding simulation environments of two channel bitlevel parallel data processing engines are constructed to test functional coverage.Finally,a real deployment scenario test was performed on two physical channel bit-level parallel data processing engine.In addition,some relevant information about the deployment test environment was given.Through the simulation environment test,the PUSCH bit-level parallel processing engine throughput reached 2.65 Gbps.Furthermore,the PDSCH bitlevel parallel processing engine throughput reached 6.14 Gbps.