Research And Design Of Digital Outphasing Transmitters Using High Efficiency Power Amplifiers

With the rapid development of digital signal processing and semiconductor technologys,the digital signal processing technology has been introduced in wireless communication.For a digital wireless transmitter,the signal processing and modulatation in the digital domain without using any analog devices.In this case,the wireless systems can change the working modes,such as the operating frequencies and signal channels,by redefining the software parameters using the same hardware.Comparing to conventional analog transmitters,the digital front-end solutions has advantages of high integration,miniaturization,and flexible configuration.Due to the limitation of spectrum resources and users demands,the peak-toaverage ratio of modulated signals is getting higher.Therefore,it's of great significance to conduct researches on digital transmitters that peform high efficiency and linearity.The Outphasing transmitter can improve efficiency while ensuring system linearity,which indicates obvious advantages and potential in wireless communications.The main works of this thesis are as follows:First,an FPGA-based all-digital outphasing signal separation and modulation method is proposed,which solves the problems of phase asymmetry and inflexible configuration traditional solutions by verilog hardware language,a digital circuit with the ablility of outphasing signal separation and modulation is implemented on FPGA.Second,an outphasing power amplifier with a center frequency of 1GHz based on the Chireix's power combiner is designed and implemented,which can improve the back-off efficiency by introducing susceptance compensation to each branch power amplifiers.The prototype provides drain efficiencies higher than 60% at 7.5d B back-off with 1 GHz continuous wave.Third,a novel design method of outphasing power combiner based on load pull and network synthesis is proposed.For verification,a new outphasing power amplifier with a center frequency of 1GHz is implemented which is tested with digital signal generated on FPGA.Compared with the Chireix's outphasing power amplifier,the design method is very simple,that can optimize the design process.The proposed power amplifiers can maintain high backoff efficiency when amplifiering high peak-to-average ratio signal.The prototype provides drain efficiencies higher than 60% at 8d B back-off with 1 GHz continuous wave.