Design And Application Of Error Control Coding In BRAM And Solid-State Storage Systems

This paper is mainly composed of two engineering practice projects during the period of personal postgraduates.The core of the research is Error control code in semiconductor memory and anti-irradiation reinforcement design.In the first part,based on the design of error correction and system level anti-radiation reinforcement of BRAM module embedded in Virtex-5 FPGA,36 k BRAM is designed to be widely used in CPU,memory and other common(72,64)Hamming parity codes for error correction and detection in the routine use of BRAM.The simulation results show that(72,64)Hamming expansion code has the ability to correct 1-bit error detection and 2-bit error.In order to meet the needs of Single Event multibit upsets in the process of below 40 nm,due to the limited error correction ability and small optimization space of Hamming code,RS code which can design error correction bits independently and improve the anti-multi bit upsets ability is adopted on the premise of analyzing the mechanism of multi bit upsets in FPGA.The traditional RS code based on the polynomial division encoder algorithm and the decoder algorithm which solves the key equation as the core is more complex for BRAM to resist multi bit upsets,and the resulting area,power consumption,pipeline,parallelization,state machine level optimization still can not meet the actual use of BRAM single clock reading scenarios.Following the idea of Hamming code check matrix design,we use matrix multiplication to design RS(8,4,4),which is suitable for 512x72 bit BRAM.This method can skillfully implement the coder with only a simple XOR gate.The simulation results are consistent with the results of mathematical proof.The centralized error caused by single particle effect of BRAM memory unit has 8-bit anti-multi bit upsets ability.The number of logic gates almost the same as that of(72,64)Hamming parity check code is implemented,which greatly improves the error control mode of error correction ability.In the second part,due to the rapid increase of Solid-State Drives capacity,the basic storage unit of NAND flash,the bottom storage particle,is developing towards the storage of multi bit data and three-dimensional stacking.The problem of high error caused by the decline of the reliability of data storage needs to be resolved.Based on the analysis of various error mechanisms and models of random telegraph noise,inter cell interference,retention noise and so on,which cause high bit error rate of NAND flash,domestic and foreign scholars have done a variety of coding and decoding designs for LDPC algorithm in NAND flash controller module of solid-state memory master controller based on this error feature.Based on the analysis of the relationship between the original error rate and the data storage time by testing Miron 64 GB MLC on flash test platform,a model for the standard deviation of the probability density distribution function of MLC NAND flash threshold voltage caused by resident error in the period of 0-1 year is derived.Based on the analysis of the model,the relationship between the number of soft information read by extra line voltage and the original bit error rate of the channel is more suitable to be read by two operations.This paper analyzes the confidence probability transfer rule of NAND flash input and output channel model,maximizes the average mutual information of input and output channel to obtain the overlapping distance of threshold voltage probability density curve distribution,and takes this distance as the reading voltage setting range of LDPC soft decision decoding to optimize the reference voltage value of LDPC soft decision decoding and obtain the most accurate soft information.The algorithm simulation experiment compares the performance of classic BP algorithm,modified MS algorithm,layered algorithm and BP and MS adaptive algorithm based on MI optimization.The simulation results show that this method is accurate,effective and adaptive for LDPC soft decoding decision decoding,and can achieve lower bit error rate than the traditional method under limited soft decision voltage precision,which is beneficial to reduce retry in LDPC soft decision decoding The number of times reduces the delay and decoding complexity caused by multiple read operations on the premise of effectively ensuring data reliability.