RTL Design And Implement Of High-speed Serial SCSI Interface

SAS(Serial Attached SCSI)interface is a result of the replacement and upgrade of traditional parallel SCSI transport interface.Compared with old generation SCSI,it has superior performance and stronger compatibility,better scalability and reliability.Downward compatible with the same type of serial transmission interface-SATA interface,it has more technical advantages,namely easier to expand the bandwidth,widely used in lager-scale storage devices,especially in the enterprise market.Nowadays,the SAS market is still in the Process of rising development It dominates enterprise market,And most storage equipment manufacturers are unable to design and produce SAS controllers in the domestic market.In this context being able to design and own a SAS controller is important.The main content of this dissertation is introduced by the background and development status of the storage interface.The following three parts are introduced: SAS protocol analysis,controller structure implementation and experimental simulation.The first part of this paper is SAS protocol analysis,which mainly involves the introduction of the overall and hierarchical structure of SAS,then analysis and description of the important functions of each layer.The second part of the paper is the structure realization of the controller,which mainly elaborates the core of this paper,the main work is to design and implement SAS 3.0 interface circuit based on FPGA platform,modularize the whole hardware circuit,complete independent RTL IP core by the HDL,and supplement important functional modules.It is described by code and conversion diagram.The specific layering is mainly divided into protocol transmission layer,PL port layer,protocol link layer and Phy control layer.In the protocol introduction and circuit implementation,this paper focuses on the description and design of SSP protocols.In the simulation test part,this paper focus on the design of the SAS controller is simulated and tested,analyze the experimental results waveform.After the simulation is completed,the design results need to be based on the FPGA board level test,the signal waveform which captured for logic analysis and the test results of its performance and stability,verify the validity and effectiveness of the entire design.In the end,the paper summarizes the meaning of the full article,and points out the inadequacies based on the experimental results and gives suggestions for improvement.The final test results show that the SAS controller works stably and the overall performance reaches the expected effect of the experiment,which has certain practical value.