The Verification Of Serial SCSI Interface Control Module Based On UVM

In the last decade,the integrated circuit(IC)has been greatly developed.With the prediction of Moore's Law,the scale and integration of chips have become higher and higher.Highly integrated chips have a wider range of uses,but also bring greater challenges to the design of the chip,and chip verification as a vital part of the chip design work,throughout the entire chip design process in.Compared with traditional verification methods,Universal Verification Methodology(UVM)has a more compact code style and reusability,which makes it more suitable for large-scale chip verification.Through the analysis of the application layer,transport layer,port layer,link layer,phy layer and physical layer of the SAS(Serial Attached SCSI)protocol,this paper studies the operation of the internal state machine of the SAS protocol and its processing of data,such as 8b/10 b encoding,scrambling and CRC checking,and on this basis,implement UVM components such as interface,transcation,sequence,driver,monitor,reference model and scoreboard,and use these components to build UVM verification platform of serial SCSI interface control module.After the verification platform is built,in order to verify the transmission function of the serial SCSI interface control module for address frames,data frames,command frames and response frames,the test cases are written and run,and the verification results are obtained.Through the analysis of the verification results,it is confirmed that the design of the serial SCSI interface control module satisfies the functional requirements of the SAS protocol for data transmission.Finally,the coverage of the code is tested to ensure the integrity of the verification platform.Compared with the traditional verification method,the verification platform has the advantages of simplicity,reusability,and portability,and these advantages are required for large-scale chip verification today.