Silicon-Based Millimeter Wave Low Noise Amplifier And Power Amplifier Design

In recent years,with the rapid development of wireless/limited communication technology,low-frequency spectrum resources have become increasingly scarce,while millimeter-wave bandwidth is large and spectrum resources are abundant,making millimeter-wave communication technology become the current research hotspot.At the same time,the rapid development of silicon-based CMOS technology has promoted the research and development of millimeter-wave communication circuits with low cost and integrated baseband/or signal processing circuits.As two key modules of communication front-end circuit,low noise amplifier and power amplifier are indispensable.Their performance directly affects the data and information quality of wireless/wired communication.However,the large loss of silicon-based millimeter-wave passive devices and the low gain of active devices bring great challenges to the design of millimeter-wave low noise amplifier and power amplifier.Based on silicon-based CMOS technology,this paper focuses on the research and design of broadband millimeter-wave low noise amplifier and power amplifier.Through the analysis of typical broadband amplifier structure and gain enhancement technology and passive devices working in millimeter wave band,millimeter wave low noise amplifier and power amplifier working in 80-101 GHz and 115 GHz-155 GHz are designed respectively.The main contents and contributions are as follows:(1)A four-stage cascade low noise amplifier is proposed,and the cascade structure noise is considered.For the problem of poor performance,the artificial transmission line inductance is introduced between the common source level and the common grid level to optimize the noise performance.In the 75GHz-110 GHz band,the noise performance is improved by about 0.6-1.3d B.The simulation results show that the 3-d B bandwidth of the low noise amplifier is 80 GHz-101 GHz,the gain is 17 d B,the noise figure is less than 8 d B,the DC power consumption is 24 m W,and the circuit area is 560 ?m x 410 ?m.(2)A two-stage cascode differential structure power amplifier is designed for parasitic grid leakage of transistors.The effect of capacitive Cgd on gain and bandwidth performance of power amplifier is eliminated by capacitive cross neutralization technology.The simulation results show that the 3-d B bandwidth of the amplifier is 115 GHz-155 GHz,the gain is 15 d B,the saturated output power Psat 10.7 d Bm,the output 1d B compression point P1 d B is 6 d Bm,the peak power additional efficiency PAE is 4.8%,the power consumption is 99.1 m W,and the circuit area is 620 ?m x 439 ?m.