Research And Implementation Of Image Enhancement Algorithm Of Anisotropic Model Based On FPGA

With the development of image sensors in biomedicine,machine vision,industrial detection and other fields,image enhancement algorithm of anisotropic diffusion models based on partial differential equations have been widely used.The function and efficiency required by the sensor module are continuously improved,which make the improvement of the image enhancement algorithm of anisotropic diffusion model an important issue.After analyzing the limitations of the Perona-Malik model a kind of the anisotropic diffusion model,three flaws were found out and could be improved,including the poor enhancement of the result's edge details,the serious decrease of the result's contrast and brightness,and the low timing utilization of iterative calculation process.To solve the above problems,the main contents of the research as follows:1.To compensate for the defect that the edge details are not well enhanced,a sharp function combined by the traditional Perona-Malik model's diffusion function is proposed in the research,according to the idea of the inverse thermal diffusion equation in the Laplace image enhancement algorithm.The transformation function performs different operations in the edge area and non-edge area,so it could achieve the role of enhancing edge detail information.2.In view of the serious decrease of the result's contrast and brightness,the logarithmic transformation processing is put before the improved Perona-Malik model algorithm processing,which can compress the high gray value area of the image and expand the low gray value area,so as to increase the contrast and grayscale means.3.In order to solve the problem that the low timing utilization of iterative calculation process,the hardware modular design of the algorithm based on FPGA is proposed since the traditional computer processing methods have been difficult to meet the hardware acceleration and real-time implementation of the algorithm.The calculation process is simplified by using a look-up table.The line and frame buffer operations are performed with the help of FIFO and DDR3 external memory chips based on the state machine design.The algorithm calculation process is designed based on pipeline processing,and the accuracy of the numerical calculation is ensured by the complement fixed-point decimal method.The hardware result is implemented by Modelsim and Vivado co-simulation and is compared with VS2013 software result,the results show that FPGA's implementation speed is nearly 200 times faster than computer CPU's.First,the design is compile by RTL's synthesis and implementation.Then timing analysis and pin constraints are performed on the design.And the board test is finally completed,which proves the feasibility of the algorithm hardware design.