Research On The Key Technology Of Network-on-chip Based On FPGA

With the development of information technology,the amount of data is exploding.The demand for high-speed data transmission and processing in the era of big data is becoming increasingly prominent.The network interconnection structure will gradually become the mainstream method for the development of data transmission system applications.The Network-on-Chip uses computer routing communication to realize the data transmission of the parallel network of the multi-core system.It fundamentally solves the competition for the right to use the traditional bus structure and the problem of network expansion.It is bound to become the mainstream communication architecture of the new-generation multi-core processing system.In response to the above-mentioned needs,this topic launched the research on the key technology of the Network-on-Chip through FPGA,which laid the foundation for the research and development of the Network-on-Chip multi-core processing system.This paper analyzes the basic routing technology of the Network-on-Chip by analyzing the topology,routing algorithm and switching flow control mechanism,etc.,launches the research on the key technology of the Network-on-Chip,formulates the routing method of this topic,and designs the Network-on-Chip experiment platform based on the parallel circuit characteristics of FPGA.By designing routing nodes,including routing arbitration module,flow control module,virtual channel,crossbar switch and network interface,a 2×2 2D-Mesh on-chip routing structure based on XY routing algorithm was implemented on FPGA.The transmission speed matching,port configuration,data alignment design,and data analysis design were completed through high-speed serial technology,and the inter-chip interconnect structure based on GTX was realized.Finally,a Network-on-Chip experiment platform was realized through Xilinx Kintex-7 FPGA,and the on-chip routing structure and inter-chip interconnect structure designed by this subject were verified and tested by Vivado software and experimental system.The experimental results show that in the uniform traffic mode,the data delay of the on-chip routing structure of the 100MHz working clock is 11.5 clock cycles;the effective bandwidth of each GTX inter-chip interconnect structure is 3.2Gbps.The physical channels were connected through 4 different length coaxial cables.In the test,the bit error rate is lower than 9.8×10^-13,the link eye diagram is completely opened,and the physical channel is good.