Studies On Implementation Of High-speed Serial Communication Based On FPGA

With the continuous development and integration of computer technology andcommunication technology, on one hand, the performance of computers and otherterminal devices continues to improve, speed of data processing is increasing; on theother hand, the speed of communication between computers and other terminalequipment is more and more higher speed and the speed of MODEM signalprocessing also become faster. The circuit connection and data format conversionbetween Terminal and MODEM circuit is a serial communication interface circuits.For normal serial communication circuit, because of the small size of the cache data,in a high speed communication system, the interface circuit will send interruptrequests to the terminal frequently, which will reduce the efficiency of the terminalprocessor, at the same time reduces speed of the entire communication system. In all,the traditional serial communication circuit is not conducive to high-speedcommunications.The experiment involved in this paper include a small improvement to traditionalserial communication circuit cache capacity shortcomings. The FIFO memory addedbetween computers and interface circuitry is used to store data in the cache. Due tolow power FPGA-based logic circuit design, high performance, easy to design, etc,the experimental design of the whole circuit are carried on in FPGA programmableway. Respectively, based on FPGA the experiment has designed high-speedasynchronous FIFO memory, serial communication reception and transmission circuit.By synthesis and simulation, I get ideal result from the experiment.This article focuses on insertion of high-speed FIFO memory to serial communicationinterface circuit. In the article, the second and third chapters made appropriateintroduction of the basis of standards-related knowledge of serial communication andFPGA. the chapter IV of the article, made a brief introduction to the associatedideology FIFO principle.