Analysis Of IR-drop In PDN Of Three-Dimensional Integrated Circuits

With the shrinking of chip feature size and the emergence of three-dimensional integrated circuit(3D-IC)technology,more and more transistors can be integrated in the unit area of the chip,so the problem of resistive voltage drop(IR-drop)becomes more and more serious.Nodes in power distribution network on chip(PDN)have grown to tens of millions.It takes a lot of time to simulate and calculate IR-drop noise.Over-large IR-drop will result in increased internal delay,clock jitter,and even logic errors,affecting the function of the chip.Three-dimensional power distribution network(3D-PDN)is a power supply network located inside the three-dimensional chip,which is used to provide stable voltage to transistors on the chip.It is also the source of IR-drop in the three-dimensional chip.Therefore,how to quickly calculate and reduce IR-drop in 3D-PDN has become an important goal in 3D-IC design.In this paper,an equivalent model of 3D-PDN is established,which consists of multi-layer power distribution network(PDN),TSV and micro-welding balls between network layers.The equivalent models of TSV,micro-solder ball and on-chip PDN are established by step modeling,and the parasitic parameters are extracted by formula calculation or software simulation.Finally,the interconnection is carried out according to the actual circuit structure.Compared with the traditional model,the parasitic capacitance of on-chip PDN is taken into account in the model,and the power line is modeled in segments.The validation results show that the self-impedance curves of the new model and the reference model are basically consistent within the frequency range of 0.1GHz-15 GHz,which proves that new model proposed has high accuracy.Based on the above models,the main factors affecting IR-drop are analyzed in many ways by simulation.From the perspective of TSV,this paper analyzes the impact of TSV's size,distribution density and location on IR-drop.Furthermore,from the perspective of on-chip PDN,the relationship between IR-drop and its four aspects,such as the number of chip layers,the size of PDN on the chip,the size of the power line and the size of the grid is analyzed,so as to lay a foundation for the calculation and analysis of IR-drop below.Based on the above model and simulation,this paper proposes the formula of IR-drop under the condition of TSV uniform/edge distribution and the optimization algorithm based on the number of TSV.The total voltage drop of 3D-PDN is composed of horizontal voltage drop and vertical voltage drop.The horizontal voltage drop can be obtained by integral solution in the circular coordinate system.The vertical voltage drop is derived from the vertical direction of current and the resistance value of the relevant components.The error between the calculated value of IR-drop formula and the software simulation value in this paper is not more than 5.24%,and the computation time required is very short.Based on the above formula,this paper proposes an algorithm for minimum TSV number required by 3D-PDN under the condition that the maximum IR-drop is satisfied.The algorithm uses the improved Newton method,which can calculate the number of required TSV in less iteration times,and can be used in the initial design and planning of the chip.