Multi-core DSP Parallel Architecture Design Of Time-domain SAR Imaging Algorithm In Large Squint Angle

Synthetic Aperture Radar(SAR)imaging technology of mobile platforms is an important research direction in radar imaging.However,in order to be able to observe the target in advance and get enough time for turning and motorizing of the platform,it is necessary to image in large squint.In the case,the echo signal has severe distance and dimensional coupling,which makes it impossible that the approximation condition of uniform focusing in frequency domain SAR imaging,which severely limits the focusing depth of it.The back projection(BP)imaging algorithm based on interpolation has no approximation premise,and is theoretically applicable to any squint angle and any wide-width SAR imaging.Therefore,the related research on the algorithm has practical significance.But the practical application of the algorithm is limited by its huge amount of computation.Recently,with the introduction of fast time-domain imaging algorithms,the improvement of the computing power of hardware chips and the wild application of parallel architecture based on FPGA and DSP in SAR signal processing system,it is possible to achieve for time-domain algorithms' application.Based on the high real-time requirements of the SAR processing platform,the paper starts from three aspects of algorithm,parallel architecture and interface designing and algorithm parallel implementation:(1).We analyzed the imaging model,the implementation principle and the calculations of the BP and the other extended fast algorithms,which are called FFBP.The FFBP reduce the amount of computation by sub-aperture imaging,which are at the expense of a certain image quality in exchange for an increase in computation.Finally the effectiveness of the algorithm is verified by analyzing data.(2).Based on the FFBP algorithm steps and its potential parallelism,we proposed a parallel framework of one FPGA and 4 DSPs which flow in group and Ping-Pong in groups.According to the architecture features,there are three high-speed interfaces such as SRIO,HyperLink and Ethernet are used on the hardware platform.We describe the specific software development steps,test the transmission stability and transmission rate,and finally summarize the matters need attention of three interfaces.It lays the foundation for algorithm implementation.(3).According to the modules of FFBP algorithm and the time running of each module,we allocated the processing task for each chip,and proposed a suitable parallel implementation of the algorithm on C6678.In order to accelerating the efficiency of program implementation,there are three aspects are deeply optimized including code,compiler and algorithm.Finally,the correctness and stability of the parallel architecture are verified by imaging analysis of the data.