Parallel Design Of Time-domain Imaging Algorithm And System Development For Synthetic Aperture Radar

Synthetic aperture radar(SAR)is a powerful and well-established remote sensing technique.It is capable of working day and night under all-weather conditions,and has the properties of long range and high resolution.Currently,SAR has been widely used in civil applications,such as land monitoring,ocean observation,and also in military applications,such as battlefield reconnaissance and monitoring of military motion.Compared with the traditional frequency-domain imaging algorithm,the theory of time-domain algorithm is more simple and does not make the same assumptions and approximations.We can accurately eliminate the coupling between range and azimuth,and get the SAR images without distortion.However,the application of time-domain imaging algorithms has been limited in some scenarios due to the large amount of computation.Therefore,it is significant that we exploit the performance of the radar signal processing system fully and improve the efficiency of time-domain imaging algorithm.In this context,with the TMS320C6678 multi-core DSP,we design the Fast Factorized BackProjection algorithm in parallel.After applying to the radar signal processing system,the algorithm efficiency and the imaging result are verified.Firstly,three typical time-domain imaging algorithms are introduced,including Back-Projection(BP)algorithm,Fast BackProjection(FBP)algorithm and Fast Factorized Back-Projection.This thesis analysis the processing flows and the computation of all the three algorithms.Then,aiming to the characteristics of FFBP we choose the parallel processing mode of data stream and design two different multi-core task allocation scheme for the two processing stages in the process of DSP parallel design.To meet the requirements of large computation and fast operation,the imaging system is based on multi multi-core DSP and FPGA.The thesis introduces the structure of the system and the connection between the chips,and describes the signal processing process of the system in detail.Finally,the boot mode of the multi-core DSP is elaborated specifically and the implementations of SPI boot mode are given combined with the actual application requirements.On this basis,this thesis proposes two schemes for multi-core boot loader.