A Chip Back_end Design And Verification Based On 7nm Manufacturing Process

The 7nm process has become the mainstream process for high-speed high-performance chip design.Compared with the previous process,the connection delay caused by the deep nanofeature size is as much as the standard cell.The timing convergence is more difficult,and the placement of the standard cell is proposed.More stringent requirements;higher unit integration increases the congestion of the layout,which is more likely to cause routing and design rule violations.Design rule changes brought by the new process,crosstalk effects on timing closure,timing conflicts brought by multi-corner,electromigration violation and IR drop will pose significant challenges to IC back-end design.This paper originates from a specific project of an enterprise,achieving the back-end design and verification of a high-speed graphics processing unit sub module based on the 7nm process,generates a physical layout that meets the engineering requirements and design rules,fixes all violations,and achieves the sign-off of the chip.The results are as follows:1)Complete places and routes of the 7nm process graphics processing chip clock module,including floorplan,place,CTS and routing.In this paper,according to the 7nm process design rules and project requirements,the data flow relationship of each module inside the chip is determined.In the floorplan,the location of hard macros is determined,physical cell insertion and power planning are completed.In the placement,improves standard cells placement according to the chip timing,utilization and congestion.In the CTS,completes the clock tree synthesis of the chip,analyzes the timing violation caused by the clock tree,manually adjusts the clock tree structure,and reduces global clock latency and skew,which improved timing of chip.In the routing,complete the symmetric routing of the differential signal by adjusting function cell location,and create shielding to eliminate the influence of the interconnection crosstalk on the key signals,so that the chip meets project requirements and design rules inspection.2)The ECO stage cleans up the residual violation of the chip,and the chip meets the timing convergence and physical rules.The problems of timing,design rule violations and physical rule violations in the ECO stage are all fixed.Timing conflict under different corners and data transition violation caused by the combination logic cascade are analyzed and fixed.3)Complete physical verification of the 7nm process chip to fix physical violations.Form verification at each stage of the chip back-end design to ensure the consistency of logic functions.Perform LVS check to ensure that the layout and schematic functions are consistent.For physical items like DRC,ERC,IR,EM and antenna effect and other violations are all fixed.Finally,the chip is clean and sign-off,layout database will tap out.4)For the problems happened in the back-end design process,write script files to improve the design efficiency.A model for fixing combinatorial logic cascade caused by data transition violation is proposed,which could accurately and efficiently generate Tcl commands to fix data transition violations.Write a python script to fix text violations in backend design,which could check,and batch generates repair commands to improve the ECO stage repair efficiency;The chip sub-module of this design is a clock module,the maximum clock frequency is 2.0GHz,and the size is 550?m*650?m.The layout simulation results show that the timing of the chip design converges,meets all the requirements of physical inspection,and meets the expectations of the project.The chip is clean and sign-off.This paper provides solutions to the problem of clock tree structure adjustment,symmetric routing,crosstalk shielding,timing conflict,and data transition violation in the IC back-end design process under the deep nano-process node.The analysis and summary of the 7nm process provides some support and reference for the development of IC back-end design.