Research And Design Of Hardware Trojan Based On AHB-SRAM Controller

With the rapid development of the integrated circuit industry,its products have penetrated into all aspects of national economic and social development.From small personal items such as smart phones,tablet computers,and smart boxes,to large-scale equipment such as computers,automotive electronics,and intelligent industries,it has greatly enriched the application fields of integrated circuit chips.Not only that,the country's military equipment,military communications,aerospace satellites,etc.,are also inseparable from the application of chips.However,chip design is the result of multi-party cooperation and most of our chips rely on imports,so that their security needs to be paid enough attention.Therefore,the research work of hardware Trojan design is helpful to provide a new direction for Trojan detection and establish a more comprehensive security information system.Based on the target circuit AHB-SRAM controller,this paper analyzes the existing Trojan detection technology at the RTL level,so as to put forward new requirements for the digital hardware Trojan code design rules,and optimize the Trojan counter module.Then,the circuit implementation of the target circuit,each module interface,etc.are analyzed,the circuit fragile points are marked,and nine different trigger types of hardware Trojans are designed for insertion,and the validity is verified by software simulation.Data such as power consumption and area by Design Compiler are summarized and optimized.Finally,based on hardware Trojans,a new method of IP copyright protection mechanism is proposed.In the study of hardware Trojan design,the following results are obtained:(1)Summarize the concept,classification,common design types and detection techniques of hardware Trojans.(2)Analyze the existing Trojan detection technology at RTL level,and propose new rules and specific implementation methods for Trojan code design to avoid traditional detection,avoid UCI detection and improve controllability.(3)Under the same frequency and other conditions,the Trojan counter module of binary code,Gray code and One-hot code is simulated and synthesized.Among them,for Gray code,due to its high circuit complexity,its area is 1.18 times of the binary code,which is 1.15 times of the One-hot code,but its dynamic power consumption is reduced by 20% compared with binary code;The One-hot code,which has the lowest dynamic power consumption,is 49% less than binary code,36% less than Gray code,and has a simple circuit structure with similar area to binary code.The analysis shows that the counter model encoded by the Onehot code is beneficial to improve the concealability of the Trojan,and the shortcoming of the One-hot short counting period can be effectively solved by the multi-stage series with the enable signal.(4)Design target circuit,AHB-SRAM controller,and detail the reason for selection,fault detection algorithm,circuit implementation,and interface of each module.Focus on the March C algorithm of the circuit BIST module to find out its algorithmic loopholes,and combine the target circuit to list its circuit vulnerability.(5)Based on the above code design rules and model optimization,eight different trigger types of hardware Trojans are designed to be inserted into the target circuit,including one combined logic Trojan,four counter Trojans and three FSM Trojans.The simulation verifies its effectiveness and compares and summarizes the factors such as power consumption,area,and trigger rate through the circuit synthesis report.It is concluded that the counter-type Trojan will at the expense of area and power consumption while achieving a lower trigger rate,however,the FSM-type Trojan has a certain advantage in area and power consumption while achieving a lower trigger rate.And adopting circuit multiplexing,the design can further reduce its area and power consumption.In summary,the use of FSM Trojans should be considered first when the triggering requirements are met.(6)Based on hardware Trojan,the combination of counter and FSM design achieves fixed time and specific event triggering,demonstrating its feasibility as an IP copyright protection mechanism.