A Reusable Hierarchical Image Processing Acceleration IP Verification Platform

Verification and design are inseparable.With the development of IC design,the function of the IP is gradually complicated,the verification difficulty and the workload are increasing,and verification becomes a challenging task.In order to verify the image processing IP with the same interface but different functions,a reusable hierarchical image processing acceleration IP verification platform is designed in this thesis,which effectively reduces the verification cost and improves the verification efficiency.The reusable hierarchical image processing accelerated IP verification platform built by the following three aspects:First,based on the hierarchical verification idea,the entire verification platform is divided into three levels.These three levels are the scene layer,the instruction layer,and the functional layer.The scene layer performs data preprocessing and configures the verification requirement related parameters and generates a parameter macro definition header file.The instruction layer provides multiple low-level underlying transaction processing validation components.The functional layer provides multiple complex transaction processing modules.Second,the entire verification platform can achieve multiple levels of reuse.In the first level,the verification platform implements the reusability of the underlying transaction processing verification component.In the second level,the verification platform can meet the different verification requirements of an image processing acceleration IP,so as to achieve full verification of all its function points.In the process of verifying an IP,the global configurable parameters of the verification platform can be set by configuring parameters located in the macro definition header file.In the third level,the verification platform can perform functional verification on different image processing acceleration IPs.In the process of verifying different image processing acceleration IP,by configuring the IP module selection bit located in the macro definition header file,the verification component of the verification platform can be flexibly increased or decreased.Finally,the verification platform is constituted suitable for verifying an IP.Third,this verification platform supports random input images and random excitation.On the one hand,the verification platform implements multi-frame continuous testing.On the other hand,the literacy and stimuli applied by the verification platform can be randomly generated according to the formulation strategy.Thereby,it improves the coverage of verification and maximizing the real working condition of IP.Reusable hierarchical image processing accelerated IP verification platform utilizes multi-platform co-simulation.MATLAB is used to to build the scene layer of this verification platform.And the hardware simulation verification work was carried out in conjunction with ModelSim SE-64 10.4 and ISE Design Suite 14.7.By verifying the parallel mark and eigenvalue statistics IP and the parallel large template gray morphological filter IP,it shows how the verification platform can fully verify all the function points of different IPs through flexible configuration.It not only proves the correctness of the design of the verification platform,but also uses the code coverage rate to verify the evaluation index,measure the progress of verification and drive the whole verification work.