The Design And Integration Of SAR ADC For Micro-bolometer

Micro-bolometer is a kind of non-refrigeration infrared detector,which has the advantages of low power consumption,small volume,low cost and wide bandwidth response range,and has been widely concerned in recent years.With the rapid development of CMOS integrated circuits,high integration,low power consumption,high detection sensitivity is the development trend of micro-measurement radiometer.One of the main techniques to achieve the above requirements is the digitization of the micro-bolometer,which integrates the analog-to-digital converter(ADC)with the micro-bolometer readout circuit to enable it to output numeric signals.The advantages of this method are to reduce the transmission noise,simplify the detector interface,improve the reliability and stability of the detector,and reduce the power consumption and cost of the detector.Based on the CSMC 0.18?m hybrid RF process,this paper mainly does two parts for the integration of ADC and micro-bolometer.In this paper,a 12-bit fully differential low-power mode successive approximation analog-to-digital converter(SAR ADC)is designed based on the vanadium oxide micro-measurement radiometer prepared by our group.(1)Aiming at the application of low power consumption of micro-bolometer,a new type of charge redistribution Digital mode converter(DAC)is proposed,which reduces the number of unit capacitance use and reduces the area and power consumption of DAC,by using two schemes of different reference voltages by using high codeword segment(MSB)and low code word segment(LSB),the signal-to-noise ratio is improved.(2)A high-speed low-power comparator is designed,and the circuit is composed of a pre-amplifier and a dynamic latch controlled by the clock,which has the advantages of no static power consumption,high comparison accuracy,small offset voltage and fast comparison speed.(3)A digital logic control circuit with asynchronous timing is designed,which eliminates the need for external comparison clock,small system noise and high precision.Secondly,an integrated scheme of SAR ADC and readout circuit is proposed,and a full differential operational amplifier is designed for this scheme,including two parts of main amplifier circuit and common-mode feedback circuits.The main amplifier circuit adopts a two-stage amplification structure with folding common-source common gate and common source amplifier,which has high gain and high bandwidth.The two-stage common-mode feedback circuit include two parts,one is the MOSFET in linear region feedback,another is the differential amplification feedback.The circuit output dynamic range is large,the power consumption is low,the common-mode output voltage is stable.In addition,this paper also uses the software Cadence Layout Virtuoso to carry on the layout design to the SAR ADC,the layout area is 376?mx193?m.The overall simulation result of the analog-to-digital converter is that the maximum sampling frequency is 5MSps,the Spurious-Free Dynamic range(SFDR)is 74.1dB,the effective number(ENOB)is 10.66 bit,the power consumption is 200?W,and the quality factor of Merit(FoM)is 24fJ/con-step.The full differential amplifier is simulated,the open-loop DC gain is 111.9dB,the bandwidth is 30.84 MHz,the phase margin is 65.2 degrees,and the establishment time is 258 ns.Applied to the single-end dual-end function,the common-mode output voltage is stable,the maximum differential output voltage error is 32.91?V,the nonlinearity is less than 0.0016%.