Research On Decoding Algorithms And Application Of Polar Codes

Noise interference reduce the reliability of practical communication.Channel coding guarantees the communication quality by adding redundant codes and deleting errors in decoding.Polar codes applied to 5G is a coding method based on channel polarization.Due to its low complexity of encoding and decoding and theoretically achieved channel capacity,polar codes become a hotspot in the channel coding.The successive cancellation(SC)decoding is proposed by E Arikan,and its improved successive cancellation list(SCL)decoding algorithm has remarkable decoding effect.Metrics sorting is one of crucial parts of decoding latency in SCL decoding.In order to reduce the time consumption of metrics sorting in decoding,the work of this paper is as follows:1.After analysis of the properties of SCL decoding metrics,this paper applies Alekseyev selection network to metrics sorting for the first time,and proposes two improved network,including pruned Alekseyev selection(PAS)network and simplified Alekseyev selection network(SAS).The PAS network optimizes the original network by using the metrics properties,and the latency of is greatly reduced compared with other metrics sorting structures.The SAS network simplified the original network by extracting and sorting separation to reuse the part of the structure in the sorting network,thus reducing the hardware consumption of measuring sorting.The two methods our proposed are low latency and low hardware consumption compared with the traditional Pruned Bitonic Sorting(PBS)network.Both two architectures can achieve low-latency and high-efficiency.2.The latency of existing metrics sorting increases with the number of reserved paths of SCL decoding.In order to reduce the latency of metrics sort,a parallel full comparison is applied to sorting metrics for the first time.The basic comparator is improved according to the properties of metrics and parallel full comparison sorting,so that the simplified full comparison sorting structure with reduced hardware consumption is obtained.The simplified full sorting has the advantage of low sorting latency when the consumption of hardware is similar to other sorting architectures.3.Two metric sorting methods and their improved architectures are simulated and verified by FPGA on the Xilinx ISE 14.7 platform.FPGA simulation results show that the proposed sorting structures can get correct sorting results,and have the characteristics of low latency and high efficiency.In this study,two kinds of SCL metrics sorting methods and their corresponding improved architectures are given,which reduce the decoding latency and hardware consumption of the metrics sorting and enriches the design ideas of the decoders.