The Design Of Super Area Array Uncooled Infrared Detector On WLP

Wafer-Level package technology is a new type of semiconductor device packaging technology.The package size is reduced to the chip size on the basis of the conventional package,and mass production is performed in the form of a wafer,which reduces the package cost and realizes a compact package.In this paper,the design of 2048×1536 super large area array uncooled infrared focal plane detector wafer-level package is carried out,and the overall package design,package structure design,package process design and Key process validation are carried out.The main research contents are as follows:(1)Completed the overall design of the ultra-large area array uncooled infrared detector chip-level package,including component structure design and packaging process design.In terms of component structure design,two-layer wafer structure and three-layer wafer structure device wafer-level package design were completed;CTW(Chip to wafer)and WTW(Wafer to wafer)packaging solutions were completed on the wafer-level packaging process.Designed and further completed the process design of the two programs.(2)Simulation design of wafer-level package mechanics and optics,and drawing of two-layer and three-layer wafer-level package engineering drawings.Through the mechanical and optical simulation analysis,the proper substrate thickness and bonding ring width were determined.The calculation method of the life of the vacuum packaged device was calculated based on the leak rate,and the scheme design of the getter was completed.In the structure of the two-layer wafer assembly,the lower substrate size and the upper substrate size are respectively designed,and the bonding ring width is required to be 1.5 mm,the thickness of the substrate is 0.85 mm,and the package size of the upper substrate is 44.860 mm × 41.730 mm.The package size of the substrate was 46.260 mm × 43.130 mm,and the corresponding engineering drawings were drawn.In terms of the structure of the three-layer wafer assembly,the size of the pedestal piece,the size of the window piece,the size of the wall piece were completed,and the corresponding engineering drawings were drawn.(3)The two-layer wafer CTW,WTW wafer-level packaging process flow and threelayer wafer WTW wafer-level packaging process flow design were completed.The process verification of key processes was carried out,and the experimental verification of wafer bonding ring metallization process and wafer bonding process was completed.