Research And FPGA Implementation Of FastICA Algorithm For Signal Blind Source Separation And Direct Digital Down Conversion

With the increasing number of man-made earth satellites and the rapid development of communication technology applied to space equipment,satellite spacing is becoming smaller and smaller,which resulting in increasingly dense radio signals in the actual environment.In addition,natural and man-made interference is becoming more and more serious,and such interference signals are often overlapped in the time domain and frequency domain.When the receiver does not know the prior information of the source signal,the separation of mixed signals and the removal of interference are the research contents of blind separation.In this thesis,the independent component analysis(ICA)theory of blind separation is used to separate spectrum aliasing signals.This method can effectively separate useful signals and interference signals.It is of great research value to improve the spectral efficiency of satellite systemsIn this thesis,fixed point independent component analysis(FastICA)is used to separate spectrum aliasing signals,and direct digital down-conversion(DDC)technology is used to reduce the sampling rate of signals.An improved FastICA(M-FastICA)algorithm is proposed.Firstly,this thesis introduces the basic model of Blind Source Separation,and mainly discusses the theory of Independent Component Analysis(ICA)and its classification.It focuses on the analysis of FastICA algorithm based on negative entropy,and uses the steepest descent method to improve the initial value sensitivity of the original algorithm,namely M FastICA algorithm.Then it explains the principle and composition of direct digital down conversion technology,and introduces the theory and implementation of each sub-module.Taking the spectrum aliasing of useful signals and interference signals in Beidou-3 satellite system as an example,the software simulation of FastICA algorithm is implemented in MATLAB,the Simulink model of direct digital down-conversion DDC is established,and the simulation and analysis of the cascaded whole system are completed.Finally,on Vivado 2016.1 platform,M-FastICA algorithm,DDC and their cascade system are programmed and simulated by Verilog language.Then,the whole system is verified at board level by using Xilinx Virtex 7 chip.At the same time,the theory and implementation of the basic numerical algorithm(such as basic trigonometric function,matrix singular value decomposition,etc.)in M-FastICA algorithm and the hardware implementation of M-FastICA algorithm sub-module are introduced.Aiming at the problem of large quantization error in fixed-point implementation of FPGA,the error is controlled at about 10-3 by optimizing module design.The FPGA implementation of DDC is done by calling the IP core.The M-FastICA algorithm and direct digital down-conversion DDC technology designed can realize the separation of two-channel spectrum aliasing signals and the reduction of sampling rate.The overall system can realize board level verification on FPGA development board and meet the design specifications.