Preparation Of Large Area Graphene Film And Its Application In Electronic Devices

Nowadays,integrated circuits have been the cornerstone and core of the development of information industry,which is the pillar of national and local economies.Silicon metal-oxide-semiconductor field-effect-transistors,whose feature sizes have been reduced to 14nm,are widely applied to large-scale integrated circuits.However,it has been predicted that the feature size of silicon material would reach its limit by 2020.Graphene is recognized as one of the most likely material to replace silicon among the known electronic materials.But it's difficult to achieve controllable preparation for large-scale and low-cost graphene films,especially the high mobility graphene applied to electronic field,which restricts the popularization of graphene in integrated circuits.However,the problems above may be solved with chemical vapor deposition.In recent years,the study of new electronic components based on graphene has been further promoted with the development of preparation process of graphene.The study of graphene field-effect-transistor?GFET?is of great significance for the continuation of Moore's law,the reason for which is that GFET has better response rates,higher cut-off frequencies and the continually narrowing feature size.But now,the study of GFET is still at its initial stage,and the applications of high dielectric constant materials to GFET are rare.SiO₂ is generally used as the gate insulating layer for GFET components in most researches,but it may easily lead to higher power dissipation and breakdown for its low dielectric constant.However,semiconductor materials used as gate insulating layer with high dielectric constant can not only keep the high carrier mobility and switching speed at a lower gate voltage,but also effectively reduce the probability of electron tunneling effect,such as Ta₂O₅,TiO₂,Al₂O₃.This paper realizes the controllable preparation for graphene films of high-quality with a 2-inch substrate of wafers by using low temperature plasma enhanced chemical vapor deposition.The graphene films prepared have a two-atomic layer and deposit uniformly.Besides,this paper researches the GFET which use Ta₂O₅ as the gate insulating layer for its high dielectric constant.The main works include the design of device structure,preparation for mask plate,material selection,preparation technology,electrical properties,etc.Finally,the mobility for hole carrier is about 2272cm²/?V·s?and the current on/off ratio is about 6.2at room temperature.It has demonstrated that the performance of the device studied is much better than that of GFET using SiO2 as the gate insulating layer.