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Research And Verificaion On Key Techniques For Digital Circuit Of 32 Channels MIMO

Posted on:2020-02-25Degree:MasterType:Thesis
Country:ChinaCandidate:J N ZhaoFull Text:PDF
GTID:2428330596476811Subject:Engineering
Abstract/Summary:PDF Full Text Request
With its huge advantages in channel capacity and transmission rate,MIMO(Multiple-Input Multiple-Output)has broad application prospects in civil 5G communication and military array radar.Based on the 3300?3600MHz frequency band in the 5G standard,we analyse the key indicators such as the amplitude and phase consistency,and complete the design and implementation of 32-channel MIMO digital circuit.The digital IF circuit provide a platform for the verification of the massive MIMO wireless communication system.The main work of the thesis is as follows:According to the requirements of MIMO hardware circuits,the key technical indicators of 32-channel digital intermediate frequency circuits are determined.Firstly,we investigate the research and development status of MIMO chip and hardware platform and analyze the architecture of common MIMO reference platform.The intermediate frequency,signal-to-noise ratio,spurious-free dynamic range and channel-to-channel consistency are determined according to the existing application scenarios.Then,we demonstrate the relationship between clock jitter and the signal-to-noise ratio of the AD/DA(Analog to Digital/Digital to Analog)converters,and the effect of clock synchronization performance on channel-to-channel consistency is specified.We still analyze the key indicators of the transceiver channel of the circuit,and clarify the requirements for the sampling rate of the device and the high speed serial interface data rate.The 32-channel MIMO digital IF circuit is designed and implemented.Firstly,we carry out the overall hardware structure,divide circuit into modules,and select core devices according to the indicators.Then,we budget the synchronization performance of the channel,analyze the key components in the circuit,and complete the simulation and optimization of the balun and clock circuits.Finally,we design the multi-channel synchronous reception and synchronous transmission scheme according to the device selection,determine the circuit,the configuration,clock network and power consumption and complete the circuit.The hardware platform is built to test and analyze the technical indicators of the hardware circuit transceiver and receiver channels.We first verify the function of the FPGA(Field Programmable Gate Array)and Zynq and the performance of the high-speed serial interface.Then,we test the key performance indicators of the clock and AD/DA converters.Finally,a measurement scheme of amplitude and phase is used to test the phase and amplitude consistency between channels.We analyze the test results compared with the indicator budget.This paper designs and implements a 32-channel MIMO digital IF circuit,which supports 32 channels of transmission and reception with 100MHz bandwidth,is able to achieve amplitude consistency between transceiver channels better than 0.25dB and phase stability better than 5°.The circuit satisfies the practical requirements of high-rate and beamforming,and has reference significance for the design of MIMO wireless communication hardware platform to a certain extent.
Keywords/Search Tags:AD/DA converter, Channel consistency, MIMO, Signal-to-noise ratio
PDF Full Text Request
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