32Channel,16Bit,Current-input AD Converter

Relative to another AD converter, Oversampling∑-△(Sigma delta)AD converter has the advantage of anti-interference, and high resolution, high accuracy but low cost.Since∑-△(Sigma delta)AD converter taking the standard CMOS technology, the requirement of precision to the analog circuit get lower.By increasing the complexity of the digital part to reduce the claim of the analog circuit.Transform the emphasis of design from the precision of the element to the speed of the element, so that overcome the limits caused by themselves, making a great breakthrough on accuracy. And the accuracy of conversion is an important index of performance of AD converter in the signal processing from a analog signal is converted into digital signal.This article mainly design the front-end integral part, control part and the synchronous serial interface of the32channel16bits current input∑-△(Sigma delta) AD converter. Start with the structure and principle of∑-△(Sigma delta) AD converter, And sort the relationship of the front-end integral part, the∑-△(Sigma delta) modulator,the digital filtering and the synchronous serial interface.Designed a reference voltage source that providing+4.096V reference voltage and a integral circuit with the integral time less than166.5us in the front-end integral part, then take the circuit simulation and verification by Cadence. The control part of the AD converter through the design configuration register to achieve the design requirements is mainly used to implement the control of the system clock, system reset and two integrator could continuous conversion in integral circuit. Finally the synchronous serial interface of the AD converter, based on the design idea that the cache date take the serial to parallel,and output selectly in sequence by selector,before the output take the parallel to serial by verilog to get the32channel16bit data output in turn. The function simulation of the Verilog code is carried out by ISE, and completed DClayout, time series analysis and so on in Cadence.The final results show that realize the continuous transformation design requirements of designing two integrator with each path in the front-end integral part, the simulation results of the circuit are ideal. The design idea of synchronous serial interface part is also verified, The32channel16bits data from the first channel to the32channel can output in turn to be able to achieve.