The Study Of Wideband Power Amplifier Behavioral Model And Band-limited DPD Technology

With the development of wireless communication,high data rates and large signal bandwidth have become a trend,which creates difficulties in designing radio frequency(RF)systems.As power amplifiers(PAs)play an important role in transmitters,the behavioral modeling and the linearization techniques of the PA have attracted our attention.Digital predistortion(DPD)is a popular linearization technique,which compensates the PA's nonlinearity by digital signal processing(DSP)and has a good flexibility.However,the high sampling rate of the analog-digital converter(ADC)and the high speed of DSP have become a big challenge in wideband DPD.The band-limited DPD is proposed to solve the problem,but the band-limited model can't be implemented easily because of its model structure with high order terms and a high order digital filter.In this paper,our studies mainly focus on the wideband band-limited DPD and some new models are proposed to simplify the band-limited model.Firstly,we study the band-limited nonlinear filtering model,which can simplify the Volterra series models greatly.Secondly,the band-limited canonical piecewise-linear function(CPWL)-based memory polynomial model is proposed to achieve higher modeling accuracy.Thirdly,as the band-limited dynamic deviation reduction(DDR)model can divide the nonlinear effect into the static and the dynamic,the band-limited cubic spline based DDR model is proposed.The model can reduce the order by cubic spline functions and have a good ability of spectrum extrapolation.Finally,after analyzing all models above,the band-limited CPWL DDR model is proposed and it has lower complexity and more flexibility.The model has a similar structure of the band-limited DDR Volterra series model,but it has particular advantages.On the one side,the model simplifies high order polynomials by CPWL.On the other side,the model simplifies the complex digital filter of band-limited model.The model has much fewer coefficients and less complexity,which should uses fewer resources in digital circuits.Experimental results show that good modeling and DPD performance can be achieved by those models.Besides,a baseband board is designed to test a high speed ADC with a JESD204 B interface,which can be used in future wideband DPD systems.Experimental results show that the serial data rate between ADC and FPGA can reach 4.9152 Gbps.