Design Of GM-APD Line Array Interface Circuit Based On Reverse Bias Voltage Adjustment

The Avalanche Photodiode(APD)operating under the Geiger Mode(GM)is capable of detecting single photon,so it is also known as Single Photon Avalanche Diode(SPAD).Recently,SPAD has been widely used in the field of faint light detection,such as 3D imaging,astronomical detection,and optical communication due to its high detection efficiency,small size,high integration,and easy maintenance.The interface circuit is a bridge connecting the SPAD and the Readout Circuit(ROIC).Optimizing the interface circuit is conducive to making full use of the detector performance.In order to achieve higher resolution in the imaging application,SPAD detectors are moving toward arrays.The non-uniformity of the manufacturing process inevitably leads to differences in the breakdown voltage of the SPAD array which will decrease the consistency of performance in the array.After studying the non-uniformity of the breakdown voltage in SPAD arrays,this thesis designed an interface circuit for a 1×8 SPAD liner array based on bias voltage regulation method.In the circuit,a 5-bit resistor string digital-to-analog converter(DAC)is used to provide selectable anode potentials for each detector.By changing the anode potential of the SPAD,the difference in breakdown voltage can be offset.This is helpful to obtain better consistency at the electronic characteristics of the SPAD array.A resistor and the junction capacitance of SPAD are utilized to sense the avalanche current in the quenching circuit.Reasonably setting the value of the sensing resistor can effectively avoid the miscount caused by leakage current even if it lasts for a long time,and can ensure the speed to detect the avalanche current.The bias voltage control circuit for SPAD arrays was simulated and fabricated in TSMC 0.18μm CMOS process.Both the pre-simulation and post-simulation results meet the design specifications.The test results show that the designed interface circuit can successfully detect the avalanche current,and its detection delay is less than 18 ns.The anode potential of SPAD in the linear array can be adjusted from 66.3mV to 1988 mV.The resolution is 5bit,and the step error can be controlled within-3.9mV~2.8mV.The designed circuit has been further verified by experimental results,operating with 1×8 SiC SPAD line arrays for photon counting applications.The test results reveal that the standard deviation of the dark detector rate(Dark Count Rate,DCR)in the linear array is reduced about a half when the bias voltage control circuit is employed.This proves the feasibility of the proposed bias voltage control method.