Design And Implementation Of RF Receive Board In LTE-A Air Interface Monitoring Instrument

With the maturity and commercialization of LTE-A networks and the continuous explosive growth of 4G users,operators are in urgent need of air-interface monitoring instruments.Therefore,the development of LTE-A air-interface monitoring instruments that meet the requirements of 3GPP standards and specifications can provide solutions for LTE-A product verification and network testing.As the core component of LTE-A air-interface monitoring instrument,the RF receiving board is responsible for collecting the signaling data of eNodeB and UE in the air-interface,converting them into baseband data and providing strong technical support for the research of LTE-A wireless access project.Based on the actual project,this thesis designed the RF receiving unit of LTE-A air-interface monitoring instrument,which is mainly divided into antenna receiving matrix chassis and RF receiving board.The main works involved in this thesis is as follows:1.According to the requirements of the project,several kinds of current RF receiving structures are compared and analyzed,and the zero-IF RF receiving scheme based on AD9361 is determined.According to the performance requirements of the project,the LNA chip,power regulator chip and balun are analyzed and calculated,and the device selection is completed.2.The RF front-end is encapsulated into the antenna receiving matrix chassis,and the conversion of 4 antennas inputs to 44 RF connectors outputs is completed;The internal matching is used to reduce the broadband matching complexity of the first stage LNA,attenuator and limiter are added in the LNA rear stage to protect the latter circuit from physical damage at the maximum damage-free input level;The input/output signals of the RF receiving board and the signal between AD9361 and FPGA are analyzed,and the peripheral circuit design is completed.According to the requirement that the frequency error is not higher than 0.1 ppm,the oven controlled crystal oscillator with frequency accuracy of 0.05 ppm is used to provide reference clock source.3.Multi-chip digital baseband synchronization and RF phase synchronization are performed on two AD9361 receivers.In the RF phase synchronization module,two methods are used to synchronize,one is internal local oscillator phase synchronization,and the other is external local oscillator phase synchronization.The ADF5355 is used to provide an external local oscillator for the two AD9361 chips,and a loop filter is designed based on the ADIsimPLL software;The power consumption of the main components in the circuit is estimated.Within the power supply capacity of the backplane of the chassis,the power tree of the RF receiving board is designed by using the low dropout regulator chip.4.The test environment was set up to complete the power supply test,including the no-load test and the power load test;Board-level test was completed for verifying the normal reception of AD9361 data link;RF reception performance test of the instrument was completed,including reference sensitivity test,dynamic range test,maximum receiving power test,etc.The results meet the project targets.According to the project requirements,this thesis completed the design and implementation of the RF receiving board,and builts a test platform to test and verify the performance of the receiving board.The test results show that the measured load voltage of the board is within the allowable error range,and the power module works well;The output frequency error of the clock module is 0.0036 ppm,which meets the 0.1ppm frequency error requirement of the project;The receiving frequency range of the RF receiving module is 703MHz~3800MHz,which meets all TD-LTE and LTE FDD bands specified by 3GPP;The rest results meeting the project requirements of sensitivity better than-94dBm@20MHz and-97dBm@10MHz;The test results meeting the project requirements of RF dynamic input range greater than 80 dB and maximum receivable power of-10 dBm and maximum damage-free level of 0dBm.