| Failure analysis,or FA,is a process to determine root cause of low yield and establish failure mechanism model,thereby fundamentally removing flaws in design,test or manufacture.Final goal of FA is to accelerate product learning process,shorten time-to-market and reduce cost.Fault isolation,which directly determines the success rate,is the most important part of FA.Strongly depending on failure complexity,it accounts for 50% ~ 80% of total work.Functional failures realized by scan chain such as Scan,ATPG(Automatic Test Pattern Generation)etc.are the major failures in digital IC.Since functional failures always need numerous pins,complicated conditions and scenarios to duplicate,it's not suitable to isolate them with conventional methods.In more advanced technology node with higher integration,demand on efficient and accurate isolation is sharply increasing while its implementation is much more difficult.In order to solve the problem in digital IC FA,below work has been performed:1.A fault isolation scheme based on logic diagnosis is proposed after studying the structure and mechanism of Scan chain.2.Layout-aware diagnosis experiment on stuck-at fault has been carried out in 2 products that meet the conditions.3.Diagnosis has been applied in failure analysis on more products that meet conditions.The effectiveness and efficiency of diagnosis will be verified by finial physical analysis result.4.A failure diagnosis methodology and procedure has been established by summarizing and refining existing cases including diagnosis setup,diagnosis running,diagnosis result analysis and best FA candidate selection.Through above work,aiming at digital IC FA which cannot be done before,we propose a new idea to locate failure address according to circuit behavior,the logic diagnosis method.Then it's proved that the newly developed method is highly-efficient.Failures will be quickly and accurately isolated after application of diagnosis which greatly expands engineering analysis capability.It also provides a complement to conventional failure analysis.Furthermore,the methodology makes diagnosis not rely on specific tool as well as speeds up the deployment.Taking our company as example,the diagnosis flow that compatible with Mentor and Synopsys platform has been widely applied in mainstream technology nodes at 40 nm and below,reducing at least 30% FA cycle time. |
