Design And Implementation Of Digital Filter For High-Quality Audio Codec

With the improvement of people's consumption level,the high-quality Audio Codec has gradually become the goal pursued by people.Signal-to-noise ratio(SNR),total harmonic distortion plus noise(THD+N),and in-band flatness are key parameters for measuring the fidelity of Audio Codec.In order to pursue high SNR,most ADC of audio codec chips adopt sigma-delta analog modulator to perform quantization noise shaping,and a series of digital filtering is carried out in the following circuits.Since the filter in this application uses more multipliers,hardware resources are heavily consumed,and the cascaded digital filter causes in-band signal attenuation to be severe and in-band flatness to be poor.Therefore,in high-quality Audio Codec applications,it is necessary to design a low cost digital filter circuit with good in-band flatness and high signal-to-noise ratio.This paper design a digital filter circuit suitable for high quality Audio Codec by analyzing the noise shaping of Sigma-Delta modulator and the theory of digital filter in Audio Codec.Firstly,in view of the problem that the in-band attenuation and the signal-to-noise ratio are not ideal in the traditional architecture,an architecture with the raised FIR compensation is proposed based on MATLAB modeling and simulation.The compensation filter in this architecture can effectively compensate the in-band frequency caused by the CIC filter.The attenuation,which has a low-pass FIR characteristic,allows for better stop-band attenuation.Secondly,based on the characteristics of the half-band FIR filter with zero-numbered tap coefficients,the design uses a high-order half-band FIR filter with less multiplication to further filter high-frequency noise and obtain a high-signal-to-noise ratio decoded audio signal.At the same time,the hardware implementation process of this paper introduces multiple clock domains,pipelines and other mechanisms to make the timing better optimized.For the problem of the hardware consumption of multiplication in the filter structure,the multiplexer reuse idea of low-speed parallel to high-speed serial is adopted,which can optimize the hardware overhead to a large extent.This paper is based on Verilog HDL hardware implementation and using Modelsim to complete the function simulation.The layout area of DC synthesis and ICC layout using HHGrace 0.13?m CMOS process is about 860×860?m~2.The signal-to-noise ratio is as high as 106.3dB under±0.03dB in-band flatness,and the total harmonic distortion plus noise is 100.8dB of whole system,which satisfies the design requirements of digital filters in high-quality Audio Codec.