| HEVC(High Efficiency Video Coding)mainly targets HD(High Definition)and UHD(Ultra High Definition)video applications.Employing more efficient video encoding tools,HEVC achieves about 2 times higher compression efficiency than H.264 for high quality video applications,but significantly increases the video coding complexity,especially for ME(Motion Estimation)which take up to the most computational effort in HEVC encoder.Therefore,it is quite meaningful to research the implementation of ME algorithm in order to accelerate the algorithm execution.The reconfigurable computing hardware combines the advantages of the general purpose processor and ASIC,which can be used to accelerate the computation intensive tasks with the features of flexibility,high performance,low power consumption.HEVC ME algorithm is a typical computing intensive task,so it is quite suitable to implement HEVC ME algorithm on the reconfigurable computing hardware to accelerate the algorithm execution.This thesis studys the mapping method of ME full search algorithm for HEVC on reconfigurable computing hardware,focusing on solving the problem of access conflict and data transmission time optimization.First,this thesis proposes the basic architecture which reuses SADs between PUs.Then,aiming at the mapping of the smallest PU SAD generation module,we propose two mapping methods to reduce memory access: AMS(Algorithm Mapping Structure)method and Basic Computational Unit Parallel method.Next,we explore the mapping method of the adder tree module and propose the multilevel PU processing architecture.Finally,in order to reduce memory access and data transmission time,we research the caching and reuse strategy for current block datas and reference block datas in the storage system of reconfigurable computing hardware.This thesis implements the ME full search algorithm for HEVC on the reconfigurable computing hardware,supporting 8×8 pixels search window and all symmetric motions partitions from 8×8 pixels to 64×64 pixels.This implementation can achieve the speedup ratio about 8.71.In comparison with automatic compilation,this implementation can provide more speedup.The analysis results show that the proposed method can fully use the parallel computation ability of the reconfigurable computing hardware and it can achieve reasonable speedup of ME full search algorithm for HEVC.In order to meet the requirements of real-time encoding 1920×1080@30fps HD video,we carry on the analysis of computing resources expansion according to the results of the performance test and based on this,a computing resources expansion solution for the reconfigurable computing hardware is proposed. |
