Hardware Design Of Key Modules In HEVC Encoder For Real-time Ultra-HD Applications

With the rapidly spread of high definition (HD) digital videos and the increase of video sources, the transmission and storage of video data are strong chanllenged, which leads to years of effort from Joint Collaborative Team on Video Coding to build High Efficiency Video Coding (HEVC) standard. Compared with previous standards, HEVC acquires much higher compression efficiency while introduces more complexity for implementation. Therefore, researches on the design of HEVC encoder and its key modules have both academic and industry values.In this paper, the background, basic theories and standardlization of video coding are first introduced. Key coding tools of HEVC are analysed, and the advantages of hardware video codec implementation scheme are discussed. Then, for the key modules of HEVC encoder, including Integer-pel Motion Estimation (IME), Franctional-pel Motion Estimation (FME) and Deblocking Filter (DBF), novel algorithms and architectures are proposed.●The flexible coding structure of HEVC and ultra-HD video applications leads to much complexity. To meet the throughput requirement, a search algorithm naming Parallel Clustering Tree Search, which can process various prediction units (PU) simultaneously, is proposed in this paper. And according to the correlation of motion vecters, and combined with some hardware-orinted methods, such as search center sharing and cost merging, this algorithm shares search processes between different PUs step by step.●For FME design, a pipeline structure is proposed to couple interpolation process and search process tightly. So that system performance is enhanced while the large buffer to store franctional pixels is avoided. Besides, interpolation results are shared between different search positions to decrease computational complexity. By analysing the data dependence in interpolation, processing order without data collision are processed based on the pipeline. The structure of interpolation filter is also optimized.●Compared with previous standards, DBF algorithm in HEVC is improved and simplified. Therefore, jointly optimizing system throughput and hardware cost of DBF module is important. According to the algorithm features and data dependence, a novel hybrid pipeline structure and processing unit organization as well as corresponding filtering order are proposed in this paper. Only one1-D filter and little single-port SRAM are consumed finally. Besides, a system-on-a-programmable-chip (SOPC) platform is built to verify the module.In conclusion, by employing multilevel parallel processing and pipeline, efficiently sharing data and calculation in the design, and jointly optimizing throughput and hardware cost, in-depth research and practice on real-time ultra-HD HEVC video encoder and its key modules are conducted.