Design And Implementation Of Network-on-chip Redundancy Technology

The semiconductor industry has consistently followed the development of Moore's Law in the past half century.In order to maintain the competitiveness of the chip,the number of transistors per unit area of the integrated circuit will double every two years.At present,billions of transistors have been integrated on a single chip.In order to effectively utilize the transistors on the chip,researchers have designed a multi-core processing system,but the traditional bus-based multi-core system has poor scalability,low bandwidth,and delay.High and high power consumption disadvantages.In order to avoid these shortcomings,the on-chip network introduces message exchange ideas into the chip,which has become the de facto communication standard for multi-core processors.With the continuous development of on-chip networks,multi-core chips based on onchip network interconnection have been widely used in image processing,atmospheric physics,and aerospace.However,in the face of complex space environments such as aviation and aerospace,the chip will face serious transient faults and have to consider the solution of transient fault tolerance.Redundant design is the basic method to solve transient faults.The target multi-core system is a heterogeneous multi-core system for high-density computing.As an on-chip network for inter-core communication,in the complex space environment of outer space,there is no effective redundancy protection scheme,which will cause the system to be affected by transient faults,resulting in the system being unable to operate normally.jobs.Therefore,this dissertation designs a redundant structure for the onchip network to shield the impact of transient faults on the target multi-core system.It is mainly divided into three parts:Firstly,the communication task of the on-chip network is studied,and the communication transmission characteristics of the target multi-core system are analyzed.The scheme of single-layer network fault tolerance and three-layer network fault tolerance is designed.The design of single-layer network fault-tolerant scheme meets control transactions and large quantities.The requirements of the transfer transaction also meet the fault tolerance requirements,but the performance is far less than the three-tier network architecture.Aiming at the fault-tolerant design of the three-layer network,the state network,the configuration network and the data network are respectively proposed to meet their own fault-tolerant schemes.Through the analysis of delay and throughput,the design idea and basis of the algorithm are analyzed.Then,the state network,the configuration network,and the data network are respectively designed with redundancy.According to the functions and data levels of the different layers of the network,in the state network and the configuration network,the protocol control signal is designed by using a three-mode redundancy,and the data is transmitted.Faulttolerant is adopted by the time dual-mode redundant self-checking method.In the data network,the protocol control signal is used for three-mode redundancy,and the transmission data dual-path dual-mode transmission self-checking scheme is used for fault tolerance.Finally,the fault-tolerant scheme of the target multi-core system is simulated and tested.The redundancy scheme of the design is verified by different packet injection rate and fault injection rate,and the data error-free ratio and delay are analyzed.Through experimental comparison,it can be found that for the transient fault caused by single-event flipping,the designed fault-tolerant scheme can provide nearly 99% fault-tolerant effect,which can ensure reliable communication of the system.