Quality Control Technology Research Of Large Area IC's Chip Alloy Sintering Die Bond

The reliability of integrated circuits is the basis for the stable operation of electronic systems.The electronic system puts forward higher requirements on the quality,reliability and storage life of integrated circuits,especially the quality and reliability of integrated circuit products of large-area chips need to be further improved.This topic is mainly for integrated circuit chips with an area larger than 40 square millimeters.Before the process optimization,the alloy sintered chip circuit bonding cavity area is about 30%~55%,the chip shear strength value is about 200~400N,water vapor and oxygen total.The content is ?5000PPM.After optimizing the chip sintering process,the circuit bonding void area is ?30%,the chip shear strength value is ?300N,and the total water vapor and oxygen content is ?3000PPM.The main research is as follows:Using FMEA analysis method to analyze the influencing factors of chip soldering quality,finishing the failure mode of large-area chip alloy sintered adhesive sheet,and find out the corresponding solutions.An FMEA risk analysis form that guides process optimization is developed.For the four types of failure causes such as chip shedding,bonding voids,seal failure,and internal water vapor content exceeding the standard,through theoretical analysis and test,a total of 15 major failure causes were obtained,and corresponding solutions were found through the process test.At the same time,according to the FMEA analysis method,the RPN values of various failure modes are respectively given,and the most important factors affecting the sintering quality of the alloy are found out,and the FMEA worksheet which can be used to guide the optimization of the alloy sintering process is formed.Study the process quality control and improvement technology of alloy sintered chips,reduce the bonding voids and improve the bonding strength.The research mainly includes three major aspects.The first is to study the metallization process on the back side of the chip.The main research is to increase the back-etching process after thinning,optimize the cleaning process before back gold,and use three-layer metallization process to improve the quality of the back gold layer.The second is to study the cleaning process optimization technology,through the effective ultrasonic cleaning and plasma cleaning and strict inspection of the back gold layer,the shell and the soldering piece of the chip before the bonding to ensure the surface state before the circuit is sintered.Improve the wettability of the solder and the metallization layer and the shell on the back of the chip,improve the effective bonding area,and improve the bonding quality.Finally,the optimization of chip sintering process parameters,including optimization of temperature and time process curve,control of vacuum degree,control of sintering atmosphere,optimization of welding pressure,etc.,in which the optimization of temperature and time process curves are mainly selected from suitable heating rate,sintering temperature,solder melting time and cooling method.Studying the internal water vapor and oxygen content of the package is less than 3000 PPM control technology.The internal atmosphere of the cavity is controlled from four aspects.Firstly,the appropriate packaging material is selected,and the imported ceramic shell and metal cover are selected as the packaging materials,followed by The alloy sintering process is used to pretreat the raw materials to reduce the release of harmful gases after packaging.The semi-finished product is pre-baked again to remove the water vapor and oxygen adsorbed on the circuit.Finally,the sealing process is optimized,the package atmosphere is purified,and the package is guaranteed.The circuit has good sealing properties.