Simulation And FPGA-Based Implementation Of 5G NR Downlink Synchronazation And Broadcast Channels

The 5G new radio interface is a new radio interface design standard based on orthogonal frequency division multiplexing technology and it is the basis of the next generation mobile communication technology.This technology will take over LTE in the near future,bringing convenience to people's lives.The synchronization channel of the 5G new radio interface is significantly different from that of the broadcast channel in LTE.The synchronization channel and the broadcast channel in the new radio interface constitute a synchronous broadcast resource block.Besides,the location and generation method of the time-frequency resource mapping is completely different from LTE.Both the primary synchronization signal and the secondary synchronization signal sequence are increased to twice in length of LTE,which doubles the correlation-based synchronization detection complexity.Usually the calculation of the correlation peak requires the use of a complex multiplier,which will bring great hardware resource consumption.At the same time,since a part of the broadcast channel in the synchronization and broadcast channel resource blocks is mapped to both sides of the secondary synchronization signal subcarrier,and the demodulation reference signal of the broadcast channel carries a part of the system parameters,the overall process needs to be adjusted and optimized.The synchronization channel and broadcast channel of the 5G new radio interface are simulated,and different algorithms are simulated and compared,which is very meaningful for improving the performance of the access network.The optimization of FPGA implementation which reduces hardware resource consumption and improves algorithm implementation complexity can provide reference for the implementation of 5G new radio interface synchronization channel.First of all,this paper builds a simulation platform for 5G new radio interface downlink synchronization and broadcast channel.The success detection rate of downlink synchronization and residual frequency offset are studied by simulation,and the results of different algorithms are compared.The blind detection method of the broadcast channel demodulation reference signal is given in this paper,the blind detection success rate and the broadcast channel error block rate are simulated.This paper presents the simulation results in the 4GHz carrier scenario and consults the relevant proposals for platform calibration.Aiming at the problem that the hardware resource consumption of the synchronization algorithm is too large,the primary synchronization signal detection algorithm with low resource occupancy is proposed,and the false detection rate and hardware resource consumption of the algorithm are simulated to provide reference for subsequent hardware implementation.Secondly,based on the algorithm and work flow of the simulation platform,this paper implements the FPGA for downlink synchr-onization.The development board uses the Xilinx ZYNQ-7020 chip and the RF AD9361.This implements made a complete downlink synchronization process.The primary synchronization signal detection algorithm with low resource occupation,the low-latency auxiliary synchronization signal detection algorithm in frequency domain are implemented,and the comprehensive results of the hardware platform,the overall waveform and hardware resource consumption are given.