Research And Implementation Of Cell Search For 5G System

The 5th Generation mobile communication(5G)system has formulated new protocol standards and introduced many key technologies compared to Long Term Evolution(LTE).The 5G system with large bandwidth,large connection,low delay and high reliability will support the landing of industries such as artificial intelligence,big data and the internet of things,and building an intelligent world in which everything is connected.As a key link to downlink baseband signal processing in 5G system,the communication quality of User Equipment(UE)is affected by the cell search.This thesis focuses on the research of cell identify detection,downlink time-frequency synchronization,and Physical Broadcast Channel(PBCH)reception.The Field Programmable Gate Array(FPGA)is used to realize the complete detection of Synchronization Signal and PBCH Block(SSB).The main work content and innovation is as follows:1.Five Orthogonal Frequency Division Multiplexing(OFDM)symbol synchronization algorithms are reproduced in 5G system.A ranking decision method is given to avoid the misjudgment of synchronization point in sliding symmetrical autocorrelation algorithm based on Primary Synchronization Signal(PSS).2.For the symbol synchronization deviation that may occur after down-sampling,the symbol fine synchronization is added for calibration.After analyzing the algorithm performance of the two phases of symbol synchronization,a sliding cross-correlation algorithm based on PSS was selected for the design of FPGA.Carrier frequency offset estimation algorithm simulation based on 5G system is used to distinguish performance.The group identify of the cell is obtained through the frequency domain cross-correlation detection of the Secondary Synchronization Signal(SSS).3.The channel estimation algorithm based on demodulation reference signals(DMRS)is researched and analyzed,and the least square algorithm and linear interpolation are used as the implementation scheme.After studying the functional modules of PBCH receiving and processing,the FPGA design is completed.In this thesis,an improved codeword descrambling module can reduce 75%.A PBCH reception processing based on DMRS estimation is proposed to reduce the random search of up to 8 times link processing to 1 time.4.This thesis has completed the FPGA designs and implementation of each functional module of cell search.The correctness of the scheme is verified by using Modelsim function simulation and key signals captured by Integrated Logic Analyzer(ILA).The rationality of the scheme is evaluated through performance testing,timing analysis,and resource consumption report.For 100 M bandwidth and Case C mode of SSB,the system performs downlink time-frequency synchronization(including cell identify detection)and PBCH reception processing time is 4.794 ms and 0.149 ms respectively.Error Vector Magnitude(EVM)after signal detection is 12.98%,which meets the requirement of less than 17.5%.The memory consumption rate of the chip is only 8%,and all indicators meet the requirements of project acceptance.